Patents by Inventor Chiang-Ming Chuang
Chiang-Ming Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10103235Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.Type: GrantFiled: May 11, 2017Date of Patent: October 16, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chia-Ming Pan, Chiang-Ming Chuang, Pei-Chi Ho, Ping-Pang Hsieh
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Publication number: 20180261609Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.Type: ApplicationFiled: March 13, 2017Publication date: September 13, 2018Inventors: Kuan-Wei SU, Yung-Lung HSU, Chih-Hsun LIN, Kun-Tsang CHUANG, Chiang-Ming CHUANG, Chia-Yi TSENG
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Patent number: 9997479Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer.Type: GrantFiled: January 13, 2017Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Hsien Lu, Chiang-Ming Chuang
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Publication number: 20180151519Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer.Type: ApplicationFiled: January 13, 2017Publication date: May 31, 2018Inventors: Szu-Hsien LU, Chiang-Ming Chuang
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Patent number: 9947759Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block.Type: GrantFiled: March 28, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Shih Lin, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu
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Patent number: 9899395Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.Type: GrantFiled: July 26, 2016Date of Patent: February 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Ming Lee, Po-Wei Liu, Chiang-Ming Chuang, Yung-Lung Hsu, Hsin-Chi Chen
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Publication number: 20180047740Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.Type: ApplicationFiled: August 15, 2016Publication date: February 15, 2018Inventors: Chih-Ming Lee, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu, Hsin-Chi Chen
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Publication number: 20180033796Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.Type: ApplicationFiled: July 26, 2016Publication date: February 1, 2018Inventors: Chih-Ming Lee, Po-Wei Liu, Chiang-Ming Chuang, Yung-Lung Hsu, Hsin-Chi Chen
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Publication number: 20180006046Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: September 18, 2017Publication date: January 4, 2018Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Patent number: 9768182Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: GrantFiled: May 18, 2016Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
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Publication number: 20170250188Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.Type: ApplicationFiled: February 25, 2016Publication date: August 31, 2017Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20170243946Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.Type: ApplicationFiled: May 11, 2017Publication date: August 24, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming PAN, Chiang-Ming CHUANG, Pei-Chi HO, Ping-Pang HSIEH
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Patent number: 9728543Abstract: A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.Type: GrantFiled: August 15, 2016Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming Pan, Chiang-Ming Chuang, Kun-Tsang Chuang, Po-Wei Liu, Yong-Shiuan Tsair
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Patent number: 9653302Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.Type: GrantFiled: July 31, 2015Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ming Pan, Chiang-Ming Chuang, Pei-Chi Ho, Ping-Pang Hsieh
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Publication number: 20170110466Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.Type: ApplicationFiled: May 18, 2016Publication date: April 20, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiang-Ming CHUANG, Chien-Hsuan LIU, Chih-Ming LEE, Kun-Tsang CHUANG, Hung-Che LIAO, Hsin-Chi CHEN
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Publication number: 20170032971Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chia-Ming PAN, Chiang-Ming CHUANG, Pei-Chi HO, Ping-Pang HSIEH
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Patent number: 9418948Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.Type: GrantFiled: September 29, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
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Patent number: 9263316Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.Type: GrantFiled: February 13, 2014Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yen Wu, Chiang-Ming Chuang, Ping-Pang Hsieh
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Patent number: 9252109Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.Type: GrantFiled: July 14, 2014Date of Patent: February 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
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Publication number: 20160020183Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.Type: ApplicationFiled: September 29, 2015Publication date: January 21, 2016Inventors: Chiang-Ming CHUANG, Chun Che HUANG, Shih-Chieh CHANG