Patents by Inventor Chiang-Ming Chuang
Chiang-Ming Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150228534Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.Type: ApplicationFiled: February 13, 2014Publication date: August 13, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Shang-Yen Wu, Chiang-Ming Chuang, Ping-Pang Hsieh
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Publication number: 20140322908Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.Type: ApplicationFiled: July 14, 2014Publication date: October 30, 2014Inventors: Chiang-Ming CHUANG, Chun Che HUANG, Shih-Chieh CHANG
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Patent number: 8796851Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.Type: GrantFiled: January 5, 2012Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Chun Che Huang, Shih-Chieh Chang
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Publication number: 20130175689Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chiang-Ming CHUANG, Chun Che HUANG, Shih-Chieh CHANG
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Patent number: 7986029Abstract: A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.Type: GrantFiled: November 8, 2005Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Kuang-Hsin Chen, I-Lu Wu
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Publication number: 20100314698Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Publication number: 20100273324Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.Type: ApplicationFiled: July 9, 2010Publication date: October 28, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7781316Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.Type: GrantFiled: August 14, 2007Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7687861Abstract: A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.Type: GrantFiled: October 12, 2005Date of Patent: March 30, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chii-Ming Wu, Chiang-Ming Chuang, Chih-Wei Chang
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Patent number: 7534671Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.Type: GrantFiled: March 29, 2008Date of Patent: May 19, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Liang-Kai Han
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Publication number: 20080182373Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.Type: ApplicationFiled: March 29, 2008Publication date: July 31, 2008Inventors: Chiang-Ming Chuang, Liang-Kai Han
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Patent number: 7361968Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.Type: GrantFiled: March 23, 2006Date of Patent: April 22, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chiang-Ming Chuang, Liang-Kai Han
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Publication number: 20070284678Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.Type: ApplicationFiled: August 14, 2007Publication date: December 13, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Publication number: 20070221966Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Inventors: Chiang-Ming Chuang, Liang-Kai Han
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Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Publication number: 20070102769Abstract: A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Inventors: Chiang-Ming Chuang, Kuang-Hsin Chen, I-Lu Wu
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Publication number: 20070090462Abstract: A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.Type: ApplicationFiled: October 12, 2005Publication date: April 26, 2007Inventors: Chii-Ming Wu, Chiang-Ming Chuang, Chih-Wei Chang
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Publication number: 20050280118Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: ApplicationFiled: June 18, 2004Publication date: December 22, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue