Patents by Inventor Chiang Shih
Chiang Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Publication number: 20230420395Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component is configured to receive a radio frequency (RF) signal and amplify a power of the RF signal. The second electronic component is disposed under the first electronic component. The second electronic component includes an interconnection structure passing through the second electronic component. The interconnection structure is configured to provide a path for a transmission of the RF signal.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Cheng LIN, Hung-Yi LIN, Cheng-Yuan KUNG, Hsu-Chiang SHIH, Cheng-Yu HO
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Publication number: 20230215816Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Yuan KUNG, Hsu-Chiang SHIH, Hung-Yi LIN, Chien-Mei HUANG
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Publication number: 20230215822Abstract: An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Meng-Wei HSIEH, Hung-Yi LIN, Hsu-Chiang SHIH, Cheng-Yuan KUNG
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Publication number: 20220359425Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: ApplicationFiled: May 24, 2022Publication date: November 10, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
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Patent number: 11342282Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: GrantFiled: February 21, 2020Date of Patent: May 24, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsu-Chiang Shih, Hung-Yi Lin, Meng-Wei Hsieh, Yu Sheng Chang, Hsiu-Chi Liu, Mark Gerber
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Publication number: 20220157709Abstract: A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar.Type: ApplicationFiled: November 18, 2020Publication date: May 19, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang Shih, Meng-Wei Hsieh, Hung-Yi Lin, Cheng-Yuan Kung
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Patent number: 11213277Abstract: A measuring system for measuring elasticity of biological tissue includes a mobile device and a measuring apparatus including a conducting seat and a measuring device. The conducting seat is for detachable mounting of the mobile device therein, and is adapted to abut against the biological tissue for conducting vibrations produced by the mobile device to the biological tissue to cause the biological tissue to vibrate. The measuring device includes an ultrasonic transducer to emit an ultrasound signal to the biological tissue and an elasticity analyzer to analyze an ultrasound echo signal that results from reflection of the ultrasound signal by the biological tissue which is vibrating to obtain an elasticity data of the biological tissue.Type: GrantFiled: December 9, 2019Date of Patent: January 4, 2022Assignee: National Cheng Kung UniversityInventors: Chih-Chung Huang, Pei-Yu Chen, Cho-Chiang Shih
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Publication number: 20210265280Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
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Patent number: 11037846Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.Type: GrantFiled: September 20, 2019Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Hsu-Chiang Shih, Cheng-Yuan Kung, Hung-Yi Lin
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Publication number: 20210169452Abstract: A measuring system for measuring elasticity of biological tissue includes a mobile device and a measuring apparatus including a conducting seat and a measuring device. The conducting seat is for detachable mounting of the mobile device therein, and is adapted to abut against the biological tissue for conducting vibrations produced by the mobile device to the biological tissue to cause the biological tissue to vibrate. The measuring device includes an ultrasonic transducer to emit an ultrasound signal to the biological tissue and an elasticity analyzer to analyze an ultrasound echo signal that results from reflection of the ultrasound signal by the biological tissue which is vibrating to obtain an elasticity data of the biological tissue.Type: ApplicationFiled: December 9, 2019Publication date: June 10, 2021Inventors: Chih-Chung Huang, Pei-Yu Chen, Cho-Chiang Shih
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Publication number: 20210090965Abstract: A semiconductor package structure includes a substrate, a die electrically connected to the substrate, and a first encapsulant. The die has a front surface and a back surface opposite to the front surface. The first encapsulant is disposed between the substrate and the front surface of the die. The first encapsulant contacts the front surface of the die and the substrate.Type: ApplicationFiled: September 20, 2019Publication date: March 25, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Hua CHEN, Hsu-Chiang SHIH, Cheng-Yuan KUNG, Hung-Yi LIN
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Patent number: 10903025Abstract: A keyboard with a vibration function is provided. The keyboard includes a base member, an upper cover, a basic key structure and a vibration key structure. The vibration key structure includes a control module, a vibration keycap and an isolation element. The control module is fixed on the upper cover. When the control module is triggered, a vibration key signal is generated and a vibration action is provided. The control module is covered by the vibration keycap. The vibration keycap is exposed outside the upper cover. The isolation element is arranged between the control module and the upper cover. The vibration key structure is enclosed by the isolation element, so that the energy of the vibration action from the control module is isolated.Type: GrantFiled: February 25, 2020Date of Patent: January 26, 2021Assignee: PRIMAX ELECTRONICS LTD.Inventors: Sheng-An Tsai, Chun-Che Wu, Shu-Wei Chou, Chun-Nan Su, Tzu-Chiang Shih
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Patent number: 10795767Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.Type: GrantFiled: December 26, 2018Date of Patent: October 6, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Zhi-Xian Chou, Wei-Chiang Shih
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Publication number: 20200210289Abstract: An error correcting system is provided. The error correcting system includes an error correcting code (ECC) circuit and a control circuit. The ECC circuit is configured to encode input data received from M input terminals to generate encoded data in response to a write operation, and output the encoded data. The input data includes write data associated with the write operation, and the encoded data includes the input data and associated parity data. The control circuit is coupled to at least one of the M input terminals. When the write operation is directed to a memory device having a data bit width less than M bits, the write data is inputted to a portion of the M input terminals, the control circuit is configured to provide reference data to another portion of the M input terminals, and the write data and the reference data serve as the input data.Type: ApplicationFiled: December 26, 2018Publication date: July 2, 2020Inventors: ZHI-XIAN CHOU, WEI-CHIANG SHIH
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Patent number: 10692568Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.Type: GrantFiled: September 13, 2018Date of Patent: June 23, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Shyh-Chyi Yang, Wei-Chiang Shih
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Patent number: 10692567Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.Type: GrantFiled: September 6, 2018Date of Patent: June 23, 2020Assignee: M31 TECHNOLOGY CORPORATIONInventors: Zhi-Xian Chou, Wei-Chiang Shih
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Publication number: 20200082875Abstract: A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: ZHI-XIAN CHOU, WEI-CHIANG SHIH
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Patent number: 10304765Abstract: A semiconductor device package includes a substrate, a first insulation layer, a support film and an interconnection structure. The substrate has a first sidewall, a first surface and a second surface opposite to the first surface. The first insulation layer is on the first surface of the substrate and has a second sidewall. The first insulation layer has a first surface and a second surface adjacent to the substrate and opposite to the first surface of the first insulation layer. The support film is on the second surface of the substrate and has a third sidewall. The support film has a first surface adjacent to the substrate and a second surface opposite to the first surface of the support film. The interconnection structure extends from the first surface of the first insulation layer to the second surface of the support film via the first insulation layer and the support film. The interconnection structure covers the first, second and third sidewalls.Type: GrantFiled: June 8, 2017Date of Patent: May 28, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Hua Chen, Ming-Hung Chen, Hsu-Chiang Shih
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Publication number: 20190088311Abstract: A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.Type: ApplicationFiled: September 13, 2018Publication date: March 21, 2019Inventors: Shyh-Chyi YANG, Wei-Chiang SHIH