Abstract: The present invention relates to a semiconductor structure having an integrated passive network and a method for making the same. The semiconductor structure includes a substrate which can be an interposer. The substrate can include a plurality of conductive vias. In various embodiments, the substrate includes a dielectric layer disposed thereon, the dielectric layer having an opening forming a straight hole allowing electrical connection between the passive network and the conductive via. The passive network includes a series of patterned dielectric and conductive layers, forming passive electronic components. In an embodiment, the passive device includes a common resistor coupled to a pair of inductors, each of the inductors coupled to a capacitor. In another embodiment, the passive device includes a resistor and an inductor electrically connected to each other, a bottom surface of the inductor coplanar with a bottom surface of the resistor.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract: The present invention relates to a remote controller for controlling playback of multimedia files. The remote controller includes a controller body and a receiver. By changing the inclination statuses of the controller body and pressing down the button on the external surface of the controller body, the user can remotely control playback of the multimedia files. The multimedia file playback remote controller of the present invention is small in size and thus convenient for storage.

Abstract: A TV signal processor is disclosed to include multiple signal receivers, a signal amplifier, a signal processor, signal decoder and a MINI-PCI interface. The TV signal processor further comprises a plurality of reserve pins arranged in a manner to meet a specification including the SVHS input signal pin, the CVBS input signal pin and the Audio input/output signal pin for inputting/outputting various audio/video signals. Thus, the use of MINI-PCI slots in the host may be effectively reduced and provide more convenience to the users.

Abstract: A presentation controlling device includes a presentation controller, wireless transceiver and a timer program. The presentation controller includes a warning module. The timer program is installed in the computer. The timer program is executed to provide a presentation time control interface and issue a remaining time alert signal to the presentation controller. In response to the remaining time alert signal, the warning module is enabled to issue the warning signal.

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract: The present invention relates to a remote controller for controlling playback of multimedia files. The remote controller includes a controller body and a receiver. By changing the inclination statuses of the controller body and pressing down the button on the external surface of the controller body, the user can remotely control playback of the multimedia files. The multimedia file playback remote controller of the present invention is small in size and thus convenient for storage.

Abstract: A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: An apparatus and method for layer jump braking control is disclosed. The apparatus is applied to an optical drive and generates a non-fixed braking signal according to a focusing error signal. The non-fixed braking signal is provided to a driver for outputting a corresponding driving force, thereby controlling a pick up head of the optical drive to perform a layer jump braking process. By using the non-fixed braking signal, the disadvantage of the conventional fixed braking signal, which cannot adapt to variations of optical disks and is subject to layer jump failure, can be avoided.

Abstract: A combo memory cell comprising a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract: A thermal module includes a thermal conductor and at least one first magnetic element. The thermal conductor is disposed above a carrier. In addition, the thermal module may further include at least one second magnetic element or at least one magnetically susceptible element. Either the second magnetic element or the magnetically susceptible element and the first magnetic element can produce magnetic attractive force or magnetic repulsion force therebetween. By such magnetic force, the thermal conductor can be retained with respect to the carrier, thus making contact with a heat generating component.

Abstract: Present invention provides a pointing device with a resolution-setting hotkey and a setting method thereof. The pointing device comprises a resolution-setting hotkey, a microprocessor and an optical sensor. The present pointing device has a default x-axis resolution and a default y-axis resolution and they are of the same value. By pressing the hotkey, a resolution-adjusting signal is generated to make the x-axis resolution is different from the y-axis resolution.

Abstract: A presentation controlling device includes a presentation controller, wireless transceiver and a timer program. The presentation controller includes a warning module. The timer program is installed in the computer. The timer program is executed to provide a presentation time control interface and issue a remaining time alert signal to the presentation controller. In response to the remaining time alert signal, the warning module is enabled to issue the warning signal.

Abstract: A roller function switching method is used between a mouse device and a computer system operated with a browser program. Firstly, the computer system is operated in a roller function switching mode. Then, the computer system controls the browser program to change a browsing page in response to a directional rolling signal generated by rotating the roller of the mouse device in a first function state. Afterward, the computer system controls the browser program to scroll the browsing page in response to the directional rolling signal generated by rotating the roller of the mouse device in a second function state. The roller function is switched between the first function state and the second function state in response to a function state switching signal generated by the operation of the mouse device.