Patents by Inventor Chieh-An YEH

Chieh-An YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230335600
    Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a work function layer surrounding the nanostructures. The method also includes forming spacers over opposite sides of the work function layer. The method also includes forming a first metal layer over the work function layer and sidewalls of the spacers. The method also includes forming a second metal layer surrounded by the first metal layer. The method also includes etching the first metal layer over opposite sides of the second metal layer. The method also includes forming a cap layer over a top surface and a sidewall of the second metal layer.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Lung CHENG, Huang-Hsuan LIN, Chih-Chieh YEH
  • Publication number: 20230326802
    Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 12, 2023
    Inventors: Szu-Chi Yang, Allen Chien, Tsai-Yu Huang, Chien-Chih Lin, Po-Kai Hsiao, Shih-Hao Lin, Chien-Chih Lee, Chih Chieh Yeh, Cheng-Ting Ding, Tsung-Hung Lee
  • Publication number: 20230317830
    Abstract: In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Tsung-Lin LEE, Da-Wen LIN, Chih Chieh YEH
  • Publication number: 20230317784
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin LEE, Choh-Fei YEAP, Da-Wen LIN, Chih-Chieh YEH
  • Publication number: 20230273506
    Abstract: An image capturing device includes a casing, a camera assembly, an adjustment element, a first stopping structure and a second stopping structure. The camera assembly is disposed within the casing. A portion of the camera assembly is exposed outside the casing. The adjustment element is connected with the camera assembly, and rotatable relative to the casing. As the adjustment element is rotated, the camera assembly is correspondingly rotated. The adjustment element includes a contacting structure. The first stopping structure and the second stopping structure are arranged between the casing and the adjustment element and located at different positions. When the camera assembly is switched to a horizontal photographing mode, the contacting structure is positioned at the first stopping structure. When the camera assembly is switched to a vertical photographing mode, the contacting structure is positioned at the second stopping structure.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 31, 2023
    Inventors: YUNG-TAI PAN, YI-PING HSIEH, CHUN-CHIEH YEH, YU-CHENG MA
  • Patent number: 11742352
    Abstract: A semiconductor device includes first and second source/drain structures, a channel layer, a gate structure, and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on a first side surface of the channel layer. The epitaxial layer forms a P-N junction with a second side surface of the channel layer.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
  • Publication number: 20230268337
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
  • Patent number: 11733590
    Abstract: An image capturing device includes a casing, a camera assembly, an adjustment element, a first stopping structure and a second stopping structure. The camera assembly is disposed within the casing. A portion of the camera assembly is exposed outside the casing. The adjustment element is connected with the camera assembly, and rotatable relative to the casing. As the adjustment element is rotated, the camera assembly is correspondingly rotated. The adjustment element includes a contacting structure. The first stopping structure and the second stopping structure are arranged between the casing and the adjustment element and located at different positions. When the camera assembly is switched to a horizontal photographing mode, the contacting structure is positioned at the first stopping structure. When the camera assembly is switched to a vertical photographing mode, the contacting structure is positioned at the second stopping structure.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 22, 2023
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Yung-Tai Pan, Yi-Ping Hsieh, Chun-Chieh Yeh, Yu-Cheng Ma
  • Publication number: 20230256569
    Abstract: A ring for clasping a cylindrical object includes a first element, a second element and a switch mechanism. The second element is circumferentially butted with the first element, and one end of the first element is adjacent to one end of the second element. The end of the second element has a protrusion protruding outwardly. The switch mechanism includes an abutting member adjacent to the end of the first element and configured to be rotated to abut against or move away from the protrusion of the end of the second element. When the abutting member is rotated and abuts against the protrusion of the end of the second element, the second element is fixed; when the abutting member is rotated and moves away from the protrusion of the end of the second element, the second element is released.
    Type: Application
    Filed: March 16, 2022
    Publication date: August 17, 2023
    Inventors: YUNG-TAI PAN, YI-PING HSIEH, CHUN-CHIEH YEH
  • Publication number: 20230238451
    Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Publication number: 20230207671
    Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: Zi-Ang Su, Chih Chieh Yeh, Ming-Shuan Li
  • Publication number: 20230184409
    Abstract: An optical component includes a phase diffraction grating and an amplitude diffraction grating. The phase diffraction grating includes a center concave section and a plurality of ring stages. The ring stages surround the center concave section. The center concave section and the ring stages form a cavity, where a light source is disposed in the cavity and emits the light to the optical component. Each of the ring stages has a stage surface. Each of the stage surfaces includes a plurality of ring microstructures arranged in concentric circles. The widths of each ring microstructure in at least one of the ring stages are less than the quarter wavelength of the light. The amplitude diffraction grating includes a center convex section and a plurality of ring parts. The center convex section and the center concave section are aligned. The ring parts surround the central convex section.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 15, 2023
    Inventors: Yu-Hao KUO, Yi-Shan LIN, Ching-Chieh YEH
  • Patent number: 11670551
    Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Allen Chien, Cheng-Ting Ding, Chien-Chih Lin, Chien-Chih Lee, Shih-Hao Lin, Tsung-Hung Lee, Chih Chieh Yeh, Po-Kai Hsiao, Tsai-Yu Huang
  • Patent number: 11652141
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20230134970
    Abstract: Systems and processes for generating audio books from text are provided. An example process includes, at an electronic device having one or more processors and memory: receiving a text including at least a first subset and a second subset, wherein at least a portion of the first subset overlaps with at least a portion of the second subset; determining, based on the text, a prosody for a speech output, wherein the prosody is representative of a genre; determining a semantic meaning of the text; and generating, based on the prosody and the semantic meaning, the speech output of the text.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 4, 2023
    Inventors: Ramya RASIPURAM, William BECKMAN, Ladan GOLIPOUR, David A. WINARSKY, Cheng-Chieh YEH, Weicheng ZHANG
  • Patent number: 11637099
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Wang, Ming-Shuan Li, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou
  • Patent number: 11626328
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 11621344
    Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Publication number: 20230098886
    Abstract: A power supply system and operating method thereof are provided. The power supply system includes a power generation circuit and a discharge circuit. The power generation circuit is configured to provide an output voltage at an output end when a power is started, and stop providing the output voltage when the power is off. The discharge circuit includes a capacitor, a comparison circuit, and a switch circuit. The comparison circuit is configured to compare a voltage at a detection end and the output voltage at the output end to generate a comparison result. The switch circuit is configured to discharge the output end according to the comparison result when the power is off. The power supply system and an operating method thereof provided by the disclosure can reduce loss when the power is off, so as to improve the operation quality of the circuit.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 30, 2023
    Applicant: Coretronic Corporation
    Inventors: Shan-Cheng Hsu, Tung-Min Lee, Ying-Chieh Yeh
  • Patent number: 11600719
    Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh