Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

Abstract: A semiconductor device includes a substrate, a first source/drain structure, a vertical channel layer, a gate structure, a second source/drain structure and a body epitaxial layer. The first source/drain structure is over the substrate. The vertical channel layer is over the first source/drain structure. The gate structure is on a first sidewall of the vertical channel layer. The second source/drain structure is over the vertical channel layer. The body epitaxial layer is on a second sidewall of the vertical channel layer. The body epitaxial layer and the vertical channel layer are of opposite conductivity types, and the body epitaxial layer is separated from the gate structure.

Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

Abstract: A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.

Abstract: A control method for a storage device of a driving recorder includes: planning a directory entry of a storage device according to a predetermined directory entry stored in a storage unit; planning a file allocation table of the storage device according to a predetermined file allocation table stored in the storage unit; and controlling a controller to write data to the storage device according to the directory entry and the file allocation table.

Abstract: A cloud management system and methods for operating the same provide for management of large deployments of networked devices and Internet of Things devices. The system provides multi-factor authentication of devices by the use of both permanent digital certificates installed in devices at time of manufacture and temporary cryptographic keys that may be revoked or changed as needed.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.

Abstract: A firmware security guarding method and an electronic system using the same are provided. The firmware security guarding method includes the following steps: setting at least one monitoring objective, wherein each of the at least one monitoring objective corresponds to one of at least one behavior reference file stored in a memory device of the electronic system; loading from the memory device the at least one behavior reference file corresponding to the at least one monitoring objective when booting the electronic system; and checking whether an abnormal event is included in a basic input/output system boot behavior of the electronic system according to the loaded at least one behavior reference file.

Abstract: A method for monitoring a server, a monitoring device and a monitoring system are provided. The method includes: setting a system event to be monitored from the server; setting a trigger recording mode and a predetermined recording amount for recording system information of the server; capturing the system information related to the system event from a baseboard management controller (BMC) managing the server into a storage circuit according to the trigger recording mode and the predetermined recording amount; and displaying the system information stored in the storage circuit on an user interface.

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Abstract: A method for synchronization of system management data includes steps of generating a request for system management data in response to execution of a system booting program, transmitting the request to a baseboard management controller so as to enable the baseboard management controller to transmit the system management data stored in a second storage unit to a processor; receiving the system management data from the baseboard management controller, and determining whether the system management data is complete; and when it is determined that the system management data is complete, storing at least one of the sequential packets of the system management data in a first storage unit, and proceeding with execution of the system booting program.

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.