Abstract: A hotspot communication stabilization system includes a hotspot communication stabilizer. The hotspot communication stabilizer includes a connected device address search unit and a comparator. The connected device address search unit serves to obtain at least one connection address from a communication host device at regular or irregular intervals. The connection address is an address of a peripheral communication device connected to the communication host device and is stored in a connection address table. The comparator serves to determine whether there is a missing address in the connection address table at a current time by comparing two connection addresses of the peripheral communication device at two adjacent times. The missing address is sent to the communication host device and the communication host device re-establishes a hotspot signal connection to the missing address corresponded to a corresponding peripheral communication device.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: Some implementations described herein provide a reticle cleaning device and a method of use. The reticle cleaning device includes a support member configured for extension toward a reticle within an extreme ultraviolet lithography tool. The reticle cleaning device also includes a contact surface disposed at an end of the support member and configured to bond to particles contacted by the contact surface. The reticle cleaning device further includes a stress sensor configured to measure an amount of stress applied to the support member at the contact surface. During a cleaning operation in which the contact surface is moving toward the reticle, the stress sensor may provide an indication that the amount of stress applied to the support member satisfies a threshold. Based on satisfying the threshold, movement of the contact surface and/or the support member toward the reticle ceases to avoid damaging the reticle.

Abstract: A power converter and a power conversion method are provided and capable of bus capacitor voltage balance based on inherent inductor components of the power converter. Compared with the conventional approach that adds a balance circuit, the power converter and the power conversion method can reduce a size of overall circuit and improve a power density. In addition, two relays of the power converter are configured to switch switching states such that two inductors store or release energy, thereby transmitting electrical energy between two bus capacitors and two load capacitors. The power converter and the power conversion method are able to realize energy balance and hybrid power supply and satisfy various load requirements.

Abstract: Embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. The buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.

Abstract: The present disclosure describes techniques for implementing video segmentation. A video is divided into a plurality of clips. Each of the plurality of clips comprises several frames. Axial-trajectory attention is applied to each of the plurality of clips by a first sub-model. Clip features corresponding to each of the plurality of clips are generated by the first sub-model. A set of object queries corresponding to each of the plurality of clips is generated based on the clip features by a transformer decoder. Trajectory attention is applied to refine sets of object queries corresponding to the plurality of clips by a second sub-model. Video-level segmentation results are generated based on the refined object queries.

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: An optical imaging system assembly includes seven lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. The second lens element has negative refractive power. An object-side surface of the third lens element is convex in a paraxial region thereof. An image-side surface of the fifth lens element is convex in a paraxial region thereof. The sixth lens element has negative refractive power, an object-side surface of the sixth lens element is convex in a paraxial region thereof, an image-side surface of the sixth lens element is concave in a paraxial region thereof. The seventh lens element has negative refractive power.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: An exposure tool is configured to remove contaminants and/or prevent contamination of mirrors and/or other optical components included in the exposure tool. In some implementations, the exposure tool is configured to flush and/or otherwise remove contaminants from an illuminator, a projection optics box, and/or one or more other subsystems of the exposure tool using a heated gas such as ozone (O3) or extra clean dry air (XCDA), among other examples. In some implementations, the exposure tool is configured to provide a gas curtain (or gas wall) that includes hydrogen (H2) or another type of gas to reduce the likelihood of contaminants reaching the mirrors included in the exposure tool. In this way, the mirrors and one or more other components of the exposure tool are cleaned and maintained in a clean environment in which radiation absorbing contaminants are controlled to increase the performance of the exposure tool.

Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.

Abstract: An electronic device includes pixel regions and pixel spacing regions, and includes: a display layer disposed in the pixel regions and the pixel spacing regions, and including a liquid crystal material and a dye material; and reflective layers respectively disposed in the pixel regions, and at one side of the display layer. The display layer is in a scattering state under a non-display state, and light is scattered by the liquid crystal material and absorbed by the dye material when the light passes through the display layer. The display layer in the pixel regions is in a transmissive state and the display layer in the pixel spacing regions is in a scattering state under a display state, and light passes through the liquid crystal material and the dye material in the pixel regions and is reflected by the reflective layers when the light passes through the display layer.

Abstract: A scanner generating an image file including transparency and visible light information includes: a scanning module scanning a document to generate a first signal and a second signal, wherein the first signal is representative of a composite visible light image of the document and a background element, and the second signal is representative of a transmitting light image transmitting through the document; a processor, which is electrically connected to the scanning module, and generates a final image file having first pixels and second pixels according to the first signal and the second signal, wherein the first pixels and the second pixels are arranged in a rectangular array, the first pixels are representative of a visible light image of the document, the second pixels are representative of a remaining image other than the document, and the second pixels have transmitting light channel values greater than 0%; and an output port being electrically connected to the processor and outputting the final image fil

Abstract: A method and a system for dynamically tuning thermal design power and a non-transitory computer-readable storage medium are described. The system is configured to dynamically tune turbo boost mode operation parameters of a central processing unit (CPU), independent of related settings of a turbo boost operation state of the CPU. In an embodiment, a controller is configured to send a power tuning signal to a basic input/output system (BIOS) to directly intervene and tune a real-time operating power of the CPU.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.