Patents by Inventor Chieh Chen

Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240219686
    Abstract: A lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. The first lens is with negative refractive power. The second lens is with refractive power. The third lens is with positive refractive power and includes a convex surface facing an image side. The fourth lens is with positive refractive power and includes a convex surface facing an object side. The fifth lens is with refractive power. The sixth lens is with refractive power. The first lens, the second lens, the third lens, the fourth lens, the fifth lens, and the sixth lens are arranged in order from the object side to the image side along an optical axis.
    Type: Application
    Filed: December 6, 2023
    Publication date: July 4, 2024
    Inventors: Wen-Chieh Chen, Yu-Wen Tai
  • Publication number: 20240206434
    Abstract: A system for testing poultry response is disclosed. The system comprises a camera, a processor, a beam generator, and a beam direction control unit. The camera is configured to receive a plurality of first images of a poultry house, and the plurality of first images include at least one of the poultry area and the background area. The processor is configured to calculate a first activity according to the plurality of first images, and to determine whether the first activity is lower than a target activity threshold. The beam generator is configured to emit a beam. The beam direction control unit is configured to move the beam. If the first activity is lower than the target activity threshold, the beam is emitted through the beam generator, and the beam is moved through the beam direction control unit, so as to disturb the plurality of poultry in the poultry house.
    Type: Application
    Filed: November 19, 2023
    Publication date: June 27, 2024
    Inventors: Kuang-fu Chang, Li-wan Huang, Ying-chieh Chen
  • Publication number: 20240213205
    Abstract: A package is provided. The package includes a carrier, a component, and a first protective element. The component is disposed over the carrier and having a side surface configured for optically coupling. The first protective element is disposed between the carrier and the component. The side surface of the component is free from being in contact with the first protective element.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Shih-Yuan SUN, Chieh-Chen FU
  • Patent number: 12021089
    Abstract: A thin film transistor substrate includes a substrate, a first conductive element and a semiconductor. The first conductive element is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The semiconductor is disposed on the substrate. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. In a top view, a virtual extending line disposes between the trace portion and the protrusive portion, the virtual extending line overlaps the second edge. At least a part of the semiconductor extends beyond the virtual extending line along a second direction vertical to the first direction.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: June 25, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Cheng-Hsiung Chen, Pei-Chieh Chen, Chao-Hsiang Wang, Yi-Ching Chen
  • Patent number: 12014966
    Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chieh Chen, Wei-Ming Wang, Ming-Lun Lee, Chih-Ren Hsieh, Ming Chyi Liu
  • Patent number: 12013730
    Abstract: A hinge synchronization module includes a base unit, and two hinge units. The two hinge units are connected to the base unit, and each of the hinge units has a gear member, a rotating platform, and a connecting member. The gear members of the hinge units mesh with each other. The rotating platform of each hinge unit has a platform body pivotable relative to the base unit. The connecting member of each hinge unit has a gear part mashing with the gear member of the hinge unit, and a slide hole. A slidable rod of the rotating platform of each hinge unit is disposed in and slidable along the slide hole of the connecting member of the hinge unit.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 18, 2024
    Assignee: FOSITEK CORPORATION
    Inventors: An-Szu Hsu, An-Wei Chung, Wei-Chieh Chen
  • Publication number: 20240196573
    Abstract: An example method for providing cooling capacity and reducing power consumption of a server assembly is disclosed. The method includes receiving temperature information corresponding to a CPU of an electrical component in the server assembly, which further includes an equipment room, and a cabinet fan module positioned adjacent to a side of the equipment room. The cabinet fan module includes electric fans therein, and the electrical component is implemented in the equipment room. The method includes determining a current power level of the CPU, and determining, using the temperature information and the current power level, a first operating speed for the electric fans. Furthermore, the method includes combining the first operating speed with a second operating speed received from a proportional-integral-derivative controller to determine a combined operating speed. The method still further includes instructing the electric fans to operate at the combined operating speed.
    Type: Application
    Filed: June 15, 2023
    Publication date: June 13, 2024
    Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Yan-Kuei CHEN, Yi-Ta HSU
  • Patent number: 12009291
    Abstract: The present disclosure provides an electronic device including a substrate, an extending element, a conductive element and a first insulating layer. The substrate includes an edge. The extending element is disposed on the substrate and includes a first conductive layer and a semiconductor layer, the first conductive layer and the semiconductor layer are overlapped, and the semiconductor layer extends to the edge of the substrate. The conductive element is overlapped with the first conductive layer. The insulating layer is disposed between the conductive element and the extending element.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: June 11, 2024
    Assignee: InnoLux Corporation
    Inventors: Chiu-Yuan Huang, Pei-Chieh Chen, Yu-Ting Liu, Tsung-Yeh Ho
  • Patent number: 12010812
    Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: June 11, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yi-Chieh Chen, Yueh-Chang Wu, Ching-Yi Shih, Po-Cheng Shen
  • Publication number: 20240188130
    Abstract: Techniques pertaining to anti-motion and anti-interference frame exchange sequences in wireless communications are described. A station (STA), such as a Wi-Fi equipment, determines to enable a frame exchange sequence (FES). The STA then communicates with one or more other STAs by utilizing the FES in which preamble puncturing sounding and data transmission are performed in a same transmission opportunity (TXOP).
    Type: Application
    Filed: October 4, 2023
    Publication date: June 6, 2024
    Inventors: Li-Chieh Chen, Kuo-Wei Chen, Chia-Jung Hsu, Yi-Hsuan Chung, Ming-Hsiang Tseng, Wei-Hsu Chen, Cheng-En Hsieh
  • Patent number: 12001616
    Abstract: A mouse device includes a lateral pressure sensing unit and a base unit having a base seat, a housing, and an inner space cooperatively defined by the base seat and the housing. The base seat is elongated in a front-rear direction, and includes a bottom face portion and an extension face portion surrounding and extending upwardly from the bottom face portion, and having spaced apart first and second lateral sections. The housing surrounds the base seat, extends upwardly from the extension face portion, and includes an operating portion extending upwardly from the first lateral section and having front, rear, upper, and lower pressing regions. The lateral pressure sensing unit is located in the inner space, is adjacent to the front, rear, upper and lower pressing regions, and is triggered upon operation on the operating portion.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: June 4, 2024
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Che-Hsun Chang, Chi-Shu Hsu, Chang-Cheng Lee
  • Publication number: 20240169236
    Abstract: The purpose of the present invention is to provide a method for calculating a VC dimension boundary in a quantum circuit, the method comprising: a step in which a computer acquires the depth L of the quantum circuit; a step in which the computer acquires the width n of the quantum circuit; and a step in which the computer identifies the VC dimension boundary in the quantum circuit on the basis of the depth L and the width n.
    Type: Application
    Filed: February 28, 2022
    Publication date: May 23, 2024
    Inventors: Masaru Sogabe, Chih-chieh Chen, Kodai Shiba
  • Publication number: 20240161323
    Abstract: The present disclosure provides a component matching and reporting method, which includes steps as follows. A 3D file is parsed to obtain features; the features is analyzed according to a feature analysis parameter to find out at least one component feature; it is judged whether the at least one component feature corresponds to a component according to a feature judgment parameter; when the at least one component feature corresponds to the component, the component is located; after the component is located, the component is measured to output a measurement report.
    Type: Application
    Filed: February 18, 2023
    Publication date: May 16, 2024
    Inventors: Ke-Min HU, Trista Pei-Chun CHEN, Chun-Hung LIN, Chun Chieh CHEN
  • Publication number: 20240161680
    Abstract: A timing controller and a polarity control method thereof are provided. The timing controller includes a line buffer and a check circuit. The line buffer temporarily stores a plurality of sub-pixel data of a current sub-pixel row in an image frame so as to transmit the plurality of sub-pixel data of the current sub-pixel row to a source driver. The check circuit generates a polarity command corresponding to the current sub-pixel row for the source driver to set a polarity inversion mode of the current sub-pixel row. The check circuit checks the plurality of sub-pixel data of the current sub-pixel row so as to determine whether to dynamically change the polarity inversion mode of the current sub-pixel row.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Li-Chieh Chen, Yen-Tao Liao
  • Patent number: 11983848
    Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: May 14, 2024
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Lung Jen, Pei-Kuei Tsung, Chih-Wei Chen, Yao-Sheng Wang, Shih-Che Chen, Yu-Sheng Lin, Chih-Wen Goo, Shih-Chin Lin, Tsung-Shian Huang, Ying-Chieh Chen
  • Publication number: 20240150017
    Abstract: A hanging structure applicable to an unmanned aerial vehicle includes a hook-shaped body and at least one hook claw. The hook-shaped body has a bottom, at least one pivoting end, and an abutting portion. A hook opening is provided between the at least one pivoting end and the abutting portion and is opposite to the bottom. In addition, the at least one hook claw has a pivoting portion, and a first claw portion and a second claw portion that extend from the pivoting portion, respectively. The pivoting portion is pivoted to the at least one pivoting end. The second claw portion is heavier than the first claw portion. When the hanging structure is in a hanging state, a first end of the first claw portion abuts against the abutting portion, and the hook opening is closed. An unmanned aerial vehicle hanging system including the above hanging structure is further provided.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Inventors: TAI-YUAN WANG, I-TA YANG, YING-CHIEH CHEN
  • Publication number: 20240151900
    Abstract: A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 9, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Li LO, Huan-Chieh CHEN, Yao-Wen CHANG, Chih-Ming CHEN
  • Patent number: 11978518
    Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chieh Chen, Cheng-Hsiung Kuo, Yu-Der Chih
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee
  • Patent number: D1028664
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 28, 2024
    Assignee: LUCKY BRAND INDUSTRIAL CO., LTD.
    Inventor: Ying-Chieh Chen