Abstract: A semiconductor device assembly is provided, which comprises a vertical stack of semiconductor devices, the vertical stack including a plurality of electrical interconnects, a plurality of retention structures, and a non-conductive film (NCF) between each adjacent pair of semiconductor devices of the vertical stack. The plurality of retention structures between each adjacent pair of semiconductor devices is disposed peripherally to the corresponding plurality of electrical interconnects. Each of the plurality of retention structures has a height less than a space between the corresponding adjacent pair of semiconductor devices, and the plurality of retention structures between each adjacent pair of semiconductor devices has a smaller first average pitch between adjacent ones of the plurality of retention structures than a second average pitch between adjacent ones of the corresponding plurality of electrical interconnects.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A system for monitoring and controlling an EUV light source includes a first temperature sensor, a signal processor, and a process controller. The first temperature sensor includes a portion inserted into a space surrounded by a plurality of vanes through a vane of the plurality of vanes, and obtains an ambient temperature that decreases with time as a function of tin contamination coating on the inserted portion. The signal processor determines an excess tin debris deposition on the vane based on the obtained chamber ambient temperature. The process controller activates a vane cleaning action upon being informed of the excess tin debris deposition by the signal processor, thereby improving availability of the EUV light source tool and reducing risks of tin pollution on other tools such as a reticle.

Abstract: A system for recording and verifying cycling activities, comprising a sensor detects a movement of a bicycle and provides distance information; a terminal device comprising a user module provides a user interface to enable a user to log in and access personal information of the user; a conversion module converts the distance information received from the sensor into carbon footprint information; a communication module transmits the carbon footprint information to a server to update a carbon footprint record associated with an account associated with at least the user or an organization; and wherein a transaction module communicating with the server or the communication module derives a carbon footprint credit based on change(s) in the carbon footprint record, wherein an account management module communicating with the server, the communication module, or the transaction module certifies or verifies the carbon footprint credit or exchange or transact in the carbon footprint credit.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: A knob structure includes a base support, a knob portion, a seat and a plurality of elastic pieces. The knob portion has an inner wall surface. The inner wall surface is inclined to an axis and surrounds the axis to define a space. The knob portion is signally connected to a processor and configured to rotate relative to the base support about the axis. The seat is at least partially located in the space. The seat is at least partially sleeved to the base support and configured to move relative to the base support along the axis. The elastic pieces are disposed on the seat and configured to abut against the inner wall surface.

Abstract: Particulate deposition rate on a photolithographic mask, particularly of tin (Sn) particles produced within an EUV light source, is reduced by producing turbulence within a radiation source chamber of the EUV light source. Turbulence can be produced by changing the temperature, pressure, and/or gas flow rate within the radiation source chamber. The turbulence reduces the number of particles exiting the EUV light source which could be deposited on the photomask.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: The present invention relates to a pharmaceutical composition comprising a weak acid drug, with the use of a bicarbonate salt to achieve a high incorporation of the drug into the liposome and a better therapeutic efficacy. Also disclosed is a method for treating a respiratory disease using the pharmaceutical composition disclosed herein.

Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Abstract: An integrated circuit includes a substrate having a semiconductor layer. The integrated circuit includes a transistor. The transistor includes stacked channels above the semiconductor layer, a first source/drain region in contact with the channels, and a second source/drain region in contact with the channels. A backside source/drain contact is positioned in the substrate directly below and electrically coupled to the first source/drain region. A frontside source/drain contact is directly above and electrically coupled to the first source/drain region. A bottom semiconductor structure is positioned below the second source/drain region and in contact with the semiconductor layer.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: A mechanical key component and a mechanical keyboard are provided. The mechanical key component includes a circuit board, an elastic element and a key cap. The circuit board is provided with a first sensing electrode. The elastic element is disposed on the circuit board, and a movable portion of the elastic element is connected to a second sensing electrode. The key cap is movably disposed on the elastic element. The elastic element enables the key cap to move between an unpressed position and a pressed position, and the movable portion drives the second sensing electrode to move relative to the first sensing electrode. In response to the key cap being moved between the unpressed position and the pressed position, a coupling capacitance between the first sensing electrode and the second sensing electrode changes to indicate whether the key cap is in the unpressed position or the pressed position.

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

Abstract: Single-stage frameworks for open-vocabulary panoptic segmentation are provided.

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.