Patents by Inventor Chieh-Jen Ku

Chieh-Jen Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220415897
    Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Juan G. Alzate-Vinasco, Travis W. LaJoie, Elliot N. Tan, Kimberly Pierce, Shem Ogadhoh, Abhishek A. Sharma, Bernhard Sell, Pei-Hua Wang, Chieh-Jen Ku
  • Publication number: 20220359759
    Abstract: Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Applicant: Intel Corporation
    Inventors: Chieh-Jen Ku, Andre Baran, Bernhard Sell, David Goldstein, Timothy Jen
  • Publication number: 20220359758
    Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Applicant: Intel Corporation
    Inventors: Shailesh Kumar Madisetti, Chieh-Jen Ku, Wen-Chiang Hong, Pei-Hua Wang, Cheng Tan, Harish Ganapathy, Bernhard Sell, Lin-Yung Wang
  • Publication number: 20220320275
    Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Juan ALZATE-VINASCO, Chieh-Jen KU, Shem OGADHOH, Allen B. GARDINER, Blake LIN, Yih WANG, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI
  • Patent number: 11462541
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Abhishek A. Sharma, Fatih Hamzaoglu, Bernhard Sell, Pei-Hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Chieh-Jen Ku, Travis W. Lajoie, Umut Arslan
  • Publication number: 20220310849
    Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Inventors: Travis W. LAJOIE, Abhishek SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Juan ALZATE VINASCO
  • Patent number: 11450669
    Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Patent number: 11404536
    Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Travis W. LaJoie, Abhishek A. Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh, Allen B. Gardiner, Blake Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Patent number: 11393927
    Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Coropration
    Inventors: Travis W. Lajoie, Abhishek Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Juan Alzate Vinasco
  • Publication number: 20220208770
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Publication number: 20220199807
    Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Noriyuki SATO, Sarah ATANASOV, Abhishek A. Sharma, Bernhard SELL, Chieh-Jen KU, Elliot N. TAN, Hui Jae YOO, Travis W. LAJOIE, Van H. LE, Pei-Hua WANG, Jason PECK, Tobias BROWN-HEFT
  • Publication number: 20220199628
    Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Noriyuki SATO, Sarah ATANASOV, Abhishek A. SHARMA, Bernhard SELL, Chieh-Jen KU, Arnab SEN GUPTA, Matthew V. METZ, Elliot N. TAN, Hui Jae YOO, Travis W. LAJOIE, Van H. LE, Pei-Hua WANG
  • Publication number: 20220189913
    Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le, Thoe Michaelos
  • Publication number: 20220189957
    Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le
  • Publication number: 20220181460
    Abstract: Disclosed herein are transistor source/drain contacts, and related methods and devices. For example, in some embodiments, a transistor may include a channel and a source/drain contact, wherein the source/drain contact includes an interface material and a bulk material, the bulk material has a different material composition than the interface material, the interface material is between the bulk material and the channel, the interface material includes indium and an element different from indium, and the element is aluminum, vanadium, zirconium, magnesium, gallium, hafnium, silicon, lanthanum, tungsten, or cadmium.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Chieh-Jen Ku, Kendra Souther, Andre Baran, Pei-hua Wang, Bernhard Sell
  • Patent number: 11329047
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-hua Wang, Chieh-jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Publication number: 20220102271
    Abstract: Tunable resistance thin film resistors for integrated circuits, related systems, and methods of fabrication are disclosed. Such tunable resistance thin film resistors include electrodes coupled to a resistive thin film that includes a base metal oxide and a second metal element. The resistors are tunable based on the concentration of the second metal element in the composition of the resistive thin film.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang
  • Publication number: 20220059704
    Abstract: Disclosed herein are transistor cap-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor cap-channel arrangement may include a channel material having a conductivity type; an insulating material; and a cap material between the channel material and the insulating material, wherein the cap material is different from the channel material and the insulating material, and the cap material has a conductivity type that is a same conductivity type as the channel material.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Applicant: INTEL CORPORATION
    Inventors: Chieh-jen Ku, Bernhard Sell, Pei-hua Wang, Christopher J. Wiegand
  • Publication number: 20210408291
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Publication number: 20210408002
    Abstract: An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Travis W. LaJoie, Abhishek A. Sharma, Van Le, Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Juan G. Alzate-Vinasco