Patents by Inventor Chieh-Jen Ku

Chieh-Jen Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366821
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Inventors: Travis LAJOIE, Abhishek SHARMA, Juan ALZATE-VINASCO, Chieh-Jen KU, Shem OGADHOH, Allen GARDINER, Blake LIN, Yih WANG, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI
  • Patent number: 11121073
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Travis Lajoie, Abhishek Sharma, Juan Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh, Allen Gardiner, Blake Lin, Yih Wang, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani
  • Publication number: 20210125992
    Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 22, 2017
    Publication date: April 29, 2021
    Inventors: Travis LAJOIE, Tahir GHANI, Jack T. KAVALIEROS, Shem O. OGADHOH, Yih WANG, Bernhard SELL, Allen GARDINER, Blake LIN, Juan G. ALZATE VINASCO, Pei-Hua WANG, Chieh-Jen KU, Abhishek A. SHARMA
  • Publication number: 20210098373
    Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Juan G. ALZATE VINASCO, Chieh-Jen KU, Shem O. OGADHOH, Allen B. GARDINER, Blake C. LIN, Yih WANG, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI
  • Publication number: 20200411426
    Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Ting CHEN, Vinaykumar V. HADAGALI
  • Publication number: 20200411520
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Yu-Wen HUANG, Shu ZHOU
  • Publication number: 20200411525
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
  • Publication number: 20200411635
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. The semiconductor device further includes a capacitor having a bottom plate above the substrate, a capacitor dielectric layer adjacent to and above the bottom plate, and a top plate adjacent to and above the capacitor dielectric layer. The bottom plate, the capacitor dielectric layer, and the top plate are within the first ILD layer or the second ILD layer. Furthermore, an air gap is formed next to the top plate and below a top surface of the second ILD layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Yu-Wen HUANG, Shu ZHOU
  • Publication number: 20200411697
    Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Chieh-Jen KU, Pei-Hua WANG, Bernhard SELL, Martin M. MITAN, Leonard C. PIPES
  • Publication number: 20200403076
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Chieh-Jen KU, Pei-Hua WANG, Bernhard SELL, Travis W. LAJOIE
  • Publication number: 20200365701
    Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG
  • Publication number: 20200350412
    Abstract: Thin film transistors having alloying source or drain metals are described. In an example, an integrated circuit structure includes a semiconducting oxide material over a gate electrode. A pair of conductive contacts is on a first region of the semiconducting oxide material. A second region of the semiconducting oxide material is between the pair of conductive contacts. The pair of conductive contacts includes a metal species. The metal species is in the first region of the semiconducting oxide material but not in the second region of the semiconducting oxide material.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG, Gregory GEORGE, Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Juan G. ALZATE VINASCO
  • Publication number: 20200303520
    Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG, Nikhil MEHTA, Shu ZHOU, Jared STOEGER, Allen B. GARDINER, Akash GARG, Shem OGADHOH, Vinaykumar HADAGALI, Travis W. LAJOIE
  • Publication number: 20200243376
    Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG, Harish GANAPATHY, Leonard C. PIPES
  • Publication number: 20200194434
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Juan G. ALZATE VINASCO, Abhishek A. SHARMA, Fatih HAMZAOGLU, Bernhard SELL, Pei-Hua WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Chieh-Jen KU, Travis W. LAJOIE, Umut ARSLAN
  • Patent number: 10658518
    Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 19, 2020
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Yicheng Lu, Wen-Chiang Hong, Chieh-Jen Ku, Kuang Sheng, Rui Li
  • Publication number: 20200105861
    Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Leif PAULSON, Kinyip PHOA, Shi LIU
  • Publication number: 20200098932
    Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Travis W. LAJOIE, Abhishek SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Juan ALZATE VINASCO
  • Publication number: 20200091156
    Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20200035683
    Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Inte Corpooration
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku