Patents by Inventor Chieh Lee

Chieh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12676181
    Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.
    Type: Grant
    Filed: July 13, 2024
    Date of Patent: July 7, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh Lee, Yi-Ching Liu, Chia-En Huang, Wen-Chang Cheng, Jonathan Tsung-Yung Chang
  • Patent number: 12675741
    Abstract: A method for training an automatic driving model comprises: obtaining a sample acquisition strategy of the automatic driving model; transmitting the sample acquisition strategy of the automatic driving model to a vehicle equipment, the vehicle equipment being configured to sort objective driving data from a driving data set based on the sample acquisition strategy; receiving the objective driving data from the vehicle equipment; adding the objective driving data into a training set of the automatic driving model; and training the automatic driving model based on the training set. A system for training the automatic driving model is also disclosed.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: July 7, 2026
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chieh Lee, Chin-Pin Kuo
  • Patent number: 12677423
    Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.
    Type: Grant
    Filed: July 11, 2024
    Date of Patent: July 7, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh Lee, Chia-En Huang, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang
  • Publication number: 20260183953
    Abstract: A method for controlling a robot, a robot and a storage medium are provided by present application. The method includes determining a motion state of the robot based on preset information corresponding to the robot; in response that the motion state is in a non-balanced state, obtaining a motion plan corresponding to the balance-assistance assembly; controlling the motion state of the robot to change to the balanced state by controlling the balance-assistance assembly to move based on the motion plan. The method may improve balance performance of the robot.
    Type: Application
    Filed: April 8, 2025
    Publication date: July 2, 2026
    Inventors: YOUNG-WAY LIU, CHIN-PIN KUO, CHIH-TE LU, JUNG-HAO YANG, TSUNG-WEI LIU, CHIEH LEE, YU-HSUAN CHIEN, YU-KAI ZHOU
  • Publication number: 20260188400
    Abstract: A method of generating an IC layout diagram includes generating a plurality of logic patterns, wherein each logic pattern corresponds to a number of bits N greater than two, arranging a column of NOR-type read-only memory (ROM) bit cells as a plurality of N-bit groups separated from each other by isolation features, assigning a pattern of the plurality of logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the plurality of logic patterns in a storage device.
    Type: Application
    Filed: February 23, 2026
    Publication date: July 2, 2026
    Inventors: Ku-Feng LIN, Chia-En HUANG, Chieh LEE, Kazumasa UNO, Ching-Wei WU
  • Patent number: 12651630
    Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.
    Type: Grant
    Filed: October 4, 2023
    Date of Patent: June 9, 2026
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ying Lee, Chieh Lee, Tung-Cheng Chang, Yen-Hsiang Huang, Chia-En Huang
  • Patent number: 12639956
    Abstract: A method for identifying road vehicles or other objects which are in motion against those which are not moving applied in an in-vehicle device of an assisted vehicle which is being driven shoots a first image of a target vehicle and a second later image of the target vehicle, determines a first mask area of the target vehicle from the first image, and determines a second mask of the target vehicle from the second image based on an instance segmentation algorithm. An Intersection over Union (IoU) is calculated between the first mask area and the second mask area and a determination made as to whether a dynamic class object mask area of the target vehicle according to the IoU should be generated. A dynamic class object mask area of the target vehicle is generated when the target vehicle is found to be a moving vehicle.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: May 26, 2026
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chieh Lee, Chin-Pin Kuo
  • Patent number: 12620239
    Abstract: A driving assistance algorithm testing method applied to an electronic device is provided. In the method, the electronic device obtains a driving assistance algorithm to be tested of a vehicle and multiple specification parameters and models a virtual scene on a simulator according to the preset parameters and generates an initial image according to the virtual scene. The electronic device obtains a target image corresponding to the driving assistance algorithm by converting the initial image according to a preset sensor conversion algorithm and the specification parameters, and generates a target vehicle control instruction according to the driving assistance algorithm, the target image, a vehicle control conversion algorithm, and the specification parameters, and scores the driving assistance algorithm by executing the target vehicle control instruction in the virtual scene of the simulator. The method can improve a verification accuracy of the driving assistance algorithm.
    Type: Grant
    Filed: May 9, 2023
    Date of Patent: May 5, 2026
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chieh Lee, Chin-Pin Kuo
  • Publication number: 20260096086
    Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface in contact with the channel layer. The first bottom surface underlaps the top surface of the gate structure across a first lateral direction. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along the first lateral direction, where the source structure has a second bottom surface facing the channel layer. The second bottom surface overlaps the top surface of the gate structure across the first lateral direction.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 2, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Chiu, Wen-Ling Lu, Ya-Yun Cheng, Yi-Ching Liu, Yih Wang, Zhiqiang Wu, Chieh Lee
  • Publication number: 20260094626
    Abstract: A circuit includes a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first sense amplifier, a first bit line transistor, and a second bit line transistor. The first memory cell is coupled to the first bit line and the first word line. The second memory cell is coupled to the second bit line and the second word line. The first sense amplifier has a first terminal. The first bit line transistor selectively couples the first bit line to the first terminal of the first sense amplifier. The second bit line transistor selectively couples the second bit line to the first terminal of the first sense amplifier.
    Type: Application
    Filed: February 3, 2025
    Publication date: April 2, 2026
    Inventors: Chen-Jun Wu, Chieh Lee, Yi-Ching Liu, Kota Shiba, Shinichiro Shiratake, Katherine H. Chiang
  • Publication number: 20260096087
    Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface facing the channel layer. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along a lateral direction, where the source structure has a second bottom surface facing the channel layer. The memory device includes a first channel pedestal and a second channel pedestals protruding from the channel layer.
    Type: Application
    Filed: January 22, 2025
    Publication date: April 2, 2026
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Chiu, Wen-Ling Lu, Ya-Yun Cheng, Yi-Ching Liu, Yih Wang, Zhiqiang Wu, Chieh Lee
  • Patent number: 12580033
    Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: March 17, 2026
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ku-Feng Lin, Chia-En Huang, Chieh Lee, Kazumasa Uno, Ching-Wei Wu
  • Publication number: 20260073970
    Abstract: The present disclosure describes a precharge circuit for a memory cell. In an example embodiment, a memory device comprises a memory array including a memory cell, a bit line connected to an output terminal of the memory cell, a reference bit line, and a sensing amplifier circuit coupled to the bit line and coupled to the reference bit line. The memory device further comprises a precharge circuit coupled to the bit line and the reference bit line.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 12, 2026
    Inventors: Chi LO, Chieh LEE, Yi-Ching LIU, Yih WANG
  • Patent number: 12530905
    Abstract: A method for managing driving applied in an electronic device which assesses distances to objects in a path of autonomous driving obtains RGB images of a scene in front of a vehicle, processes the RGB images based on a trained depth estimation model, and obtain depth images corresponding to the RGB images. The depth images are converted to 3D point cloud maps, 3D regions of interest from the 3D point cloud maps are determined according to a size of the vehicle, and the 3D regions of interest are converted into 2D regions of interest according to internal parameters of a camera. The 2D regions of interest are analyzed for obstacles. Driving continues when the 2D regions of interest have no obstacles, the vehicle is controlled to issue an alarm when obstacles are discovered.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: January 20, 2026
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chieh Lee, Jung-Hao Yang, Shih-Chao Chien, Chin-Pin Kuo
  • Patent number: 12529185
    Abstract: The present invention relates to an artificial leather and a method for producing the same. The artificial leather includes a substrate, a thermoplastic ethylene-propylene polymer elastic layer, and a surface layer. The substrate is formed from fibers having a first thermoplastic ethylene-propylene polymer. The surface layer is formed from a second thermoplastic ethylene-propylene polymer. The first thermoplastic ethylene-propylene polymer and the second thermoplastic ethylene-propylene polymer provide the substrate with a specific melting point and the surface layer with a specific melting point, respectively. By the substrate with the specific melting point and the surface layer with the specific melting point, the artificial leather has an excellent post-processability. Therefore, the artificial leather can have the substrate and the surface layer which have the same material, thereby having an excellent recyclability.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 20, 2026
    Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chien-Chia Huang, Chia-Ho Lin, Chieh Lee, Wei-Ling Chen
  • Publication number: 20250391082
    Abstract: A computing device obtains a first image depicting a facial region of a user and an object occluding a portion of the facial region of the user. The computing device generates a second image of the user without the object occluding the portion of the facial region of the user based on the first image. A selection comprising desired eyeglasses is obtained, and the computing device generates a third image comprising the desired eyeglasses rendered on the second image to perform virtual try-on of the desired eyeglasses for the user to evaluate.
    Type: Application
    Filed: June 5, 2025
    Publication date: December 25, 2025
    Inventors: Chieh LEE, Yi-Hsin LIU
  • Publication number: 20250365918
    Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir
    Type: Application
    Filed: July 31, 2025
    Publication date: November 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chung Chiu, Wei-Hua Chen, Chieh LEE, Chun-Ying LEE, Yi-Ching LIU, Chia-En Huang
  • Publication number: 20250356891
    Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.
    Type: Application
    Filed: July 30, 2025
    Publication date: November 20, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Chiao YEH, Chieh LEE, Chia-En HUANG, Ji Kuan LEE, Yao-Jen YANG
  • Publication number: 20250359024
    Abstract: A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.
    Type: Application
    Filed: July 30, 2025
    Publication date: November 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh Lee, Chi Lo, Yi-Ching LIU, Yih Wang
  • Patent number: 12472730
    Abstract: The present disclosure relates to an step artificial leather having visual penetration and a manufacturing method thereof. The artificial leather includes a thermoplastic substrate, a thermoplastic adhering layer, and a thermoplastic surface layer. The thermoplastic substrate has fiber net shape, and has visual penetration. The thermoplastic adhering layer is disposed on the thermoplastic substrate. The thermoplastic surface layer is disposed on the thermoplastic adhering layer. The thermoplastic surface layer and the thermoplastic adhering layer are transparent. Therefore, the artificial leather of the present disclosure has visual penetration effect. The product made from the artificial leather of the present disclosure has attractive appearance and diversity.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: November 18, 2025
    Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chien-Chia Huang, Tsung-Yu Tsai, Chieh Lee, Wei-Ling Chen