Patents by Inventor Chieh Lee
Chieh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11615252Abstract: A dispatcher virtual assistant (DVA) that can augment the capability of emergency dispatchers while reducing human errors. Major functions of the DVA include updating an emergency incident's status in real time, recommending or reminding the dispatcher to take proper actions at the right timing, answering the dispatcher's inquiries for task-related information, and fulfilling the dispatcher's request for an incident report. The DVA system includes a dispatcher language model based on machine-learning and deep-learning algorithms, for extracting the status of a live incident from incoming incident logs, and for processing and answering inquiries or requests from the dispatcher. It is customizable for different types of emergencies and for different local communities. The DVA can be used in tandem with an existing CAD system.Type: GrantFiled: May 13, 2021Date of Patent: March 28, 2023Assignee: D8AI Inc.Inventors: Yin-Hsuan Wei, Angela Chen, Yuh-Bin Tsai, Fu-Chieh Chang, You-Zheng Yin, Zai-Ching Wen, Pei-Hua Chen, Hsiang-Pin Lee, Richard Li-Cheng Sheng, Hui Hsiung
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Publication number: 20230090418Abstract: An electronic device including a hinge module, a first body, a second body, and a flexible display assembled to the first body and the second body is provided. Each of the first body and the second body is pivoted and slidably connected to the hinge module, and a cover of the hinge module is exposed out of the first body and the second body. The first body and the second body are rotated relatively via the hinge module to bend or flatten the flexible display, when the flexible display is bending from a flat state, a bending portion of the flexible display leans against the cover and pushes the cover away from the first body and the second body.Type: ApplicationFiled: November 30, 2022Publication date: March 23, 2023Applicant: Acer IncorporatedInventors: Yi-Ta Huang, Cheng-Nan Ling, Wu-Chen Lee, Wen-Chieh Tai, Kun-You Chuang
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Publication number: 20230086944Abstract: A format for use in encoding moving image data, comprising: a sequence of frames including plurality of the frames in which at least a region is encoded using motion estimation; a respective set of motion vector values representing motion vectors of the motion estimation for each respective one of these frames or each respective one of one or more regions within each of such frames; and at least one respective indicator associated with each of the respective frames or regions, indicating whether the respective motion vector values of the respective frame or region are encoded at a first resolution or a second resolution.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Applicant: Microsoft Technology Licensing, LLCInventors: You Zhou, Sergey Silkin, Sergey Sablin, Chih-Lung Lin, Ming-Chieh Lee, Gary J. Sullivan
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Patent number: 11609615Abstract: A portable electronic device including a first body, a second body, a first hinge connected to the first body, a second hinge connected to the second body, and a linking rod is provided. The linking rod has a first end and a second end opposite to each other, wherein the first end is pivoted to the first hinge eccentric to a rotation axis of the first hinge, and the second end is pivoted to the second hinge eccentric to a rotation axis of the second hinge. The first and the second bodies are rotated to be closed to or far away from each other by the first hinge, the second hinge, and the linking rod.Type: GrantFiled: May 13, 2020Date of Patent: March 21, 2023Assignee: Acer IncorporatedInventors: Yi-Ta Huang, Wu-Chen Lee, Cheng-Nan Ling, Wen-Chieh Tai, Kun-You Chuang
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Publication number: 20230081739Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.Type: ApplicationFiled: March 22, 2022Publication date: March 16, 2023Applicant: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Publication number: 20230073062Abstract: A method for preventing photomask contamination includes securing a photomask on a bottom surface of an electrostatic chuck; generating a first voltage at a peripheral area of the bottom surface of the electrostatic chuck to attract a particle onto the peripheral area of the bottom surface of the electrostatic chuck, wherein the peripheral area of the bottom surface of the electrostatic chuck is not directly above the photomask; after generating the first voltage, generating a second voltage at the peripheral area of the bottom surface of the electrostatic chuck to repulse the particle, wherein the first voltage and the second voltage have opposite electrical properties; and generating a third voltage, by using a collecting plate, near a sidewall of the photomask to attract the repulsed particle.Type: ApplicationFiled: November 16, 2022Publication date: March 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Chieh CHEN, Tsung-Chih CHIEN, Chih-Tsung SHIH, Tsung-Chuan LEE
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Patent number: 11601595Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.Type: GrantFiled: January 31, 2020Date of Patent: March 7, 2023Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huang, Yi-Chun Cheng
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Patent number: 11600703Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.Type: GrantFiled: January 29, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang, Shih-Ya Lin, Chung-En Tsai, Chee-Wee Liu
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Patent number: 11600543Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: GrantFiled: September 14, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
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Publication number: 20230066418Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Sheng Chieh HUANG, Cheng Kuang TSO, Chou-Feng LEE, Chung-Hsiu CHENG, Jr-Sheng CHEN, Chun Yan CHEN, Chih-Hsien HSU, Chin-Tai HUNG
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Publication number: 20230067527Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chen CHU, Chia-Tien WU, Chia-Wei SU, Yu-Chieh LIAO, Chia-Chen LEE, Hsin-Ping CHEN, Shau-Lin SHUE
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Publication number: 20230064162Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed herein including creating a photoresist mixture that includes a surfactant, and a base solvent; one or more boiling point modifying solvents having a boiling point higher in temperature than the base solvent; and one or more hydrophilicity modifying solvents that are more hydrophilic than the base solvent; depositing the photoresist mixture onto a substrate comprising a plurality of UBMLs using a wet film process; performing a pre-bake process to cure the photoresist; and patterning the photoresist.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Hsing-Chieh Lee, Hung-Jui Kuo, Ming-Tan Lee, Ting Yi Lin
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Publication number: 20230067423Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh Lee, Yi-Ching Liu, Chia-En Huang, Chang Jen-Yuan, Yih Wang
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Publication number: 20230067859Abstract: A semiconductor device includes a plurality of first channel layers vertically spaced from one another and a plurality of second channel layers vertically spaced form one another. Each of the plurality of first and second channel layers extend along a first lateral direction. The semiconductor device includes an isolation structure disposed between the plurality of first channel layers and the plurality of second channel layers along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a plurality of inner spacers discretely disposed along a first sidewall of the isolation structure that faces toward the first lateral direction, or discretely disposed along a second sidewall of the isolation structure that faces away from the first lateral direction wherein an interface between each of the plurality of inner spacers and the first or second sidewall has a vertical profile.Type: ApplicationFiled: February 15, 2022Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiaowen Lee, Ming-Ching Chang
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Patent number: 11594518Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: GrantFiled: June 3, 2021Date of Patent: February 28, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chi Lee, Jung Jui Kang, Chiu-Wen Lee, Li Chieh Chen
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Patent number: 11595667Abstract: When encoding/decoding a current block of a current picture using intra block copy (“BC”) prediction, the location of a reference block is constrained so that it can be entirely within an inner search area of the current picture or entirely within an outer search area of the current picture, but cannot overlap both the inner search area and the outer search area. In some hardware-based implementations, on-chip memory buffers sample values of the inner search area, and off-chip memory buffers sample values of the outer search area. By enforcing this constraint on the location of the reference block, an encoder/decoder can avoid memory access operations that are split between on-chip memory and off-chip memory when retrieving the sample values of the reference block. At the same time, a reference block close to the current block may be used for intra BC prediction, helping compression efficiency.Type: GrantFiled: March 11, 2021Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: You Zhou, Chih-Lung Lin, Ming-Chieh Lee
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Patent number: 11593056Abstract: An interactive exercise apparatus for allowing a user to invite a friend to join an exercise class includes a mirror display device, a communication module and a control unit. The mirror display device has a mirror configured to reflect an image of the user and a display device configured to display video content which includes an instructor image demonstrating an exercise in the exercise class. The communication module is configured to interconnect with another interactive exercise apparatus of the friend via a network. The control unit is configured to control display content and is operable to control the mirror display device to display the instructor image and a real-time image of the friend to the user. Specifically, the instructor image, the image of the friend and the image of the user reflected by the mirror are shown simultaneously on the mirror display device during the exercise class.Type: GrantFiled: August 12, 2021Date of Patent: February 28, 2023Assignee: Johnson Health Tech Co., Ltd.Inventors: Hsin-Huang Chiang, Yu-Chieh Lee, Ning Chuang, Wei-Ting Weng, Cheng-Ho Yeh
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Publication number: 20230058459Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate, a plurality of inner spacer features interleaving the plurality of nanostructures. The plurality of nanostructures are arranged along a direction perpendicular to the substrate. The plurality of inner spacer features include a bottommost inner spacer feature and upper inner spacer features disposed above the bottommost inner spacer feature. The first height of the bottommost inner spacer feature along the direction is greater than a second height of each of the upper inner spacer features.Type: ApplicationFiled: February 16, 2022Publication date: February 23, 2023Inventors: Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang, Wan-Hsuan Hsieh, Yi-Chun Liu, Chee-Wee Liu
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Publication number: 20230054243Abstract: The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.Type: ApplicationFiled: February 16, 2022Publication date: February 23, 2023Inventors: Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang, Wan-Hsuan Hsieh, Chung-En Tsai, Chee-Wee Liu
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Patent number: D979562Type: GrantFiled: January 21, 2021Date of Patent: February 28, 2023Assignee: COMPAL ELECTRONICS, INC.Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee