Abstract: The present disclosure describes a precharge circuit for a memory cell. In an example embodiment, a memory device comprises a memory array including a memory cell, a bit line connected to an output terminal of the memory cell, a reference bit line, and a sensing amplifier circuit coupled to the bit line and coupled to the reference bit line. The memory device further comprises a precharge circuit coupled to the bit line and the reference bit line.

Abstract: Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.

Abstract: A device includes a multiplication unit and a configurable summing unit. The multiplication unit is configured to receive data and weights for an Nth layer, where N is a positive integer. The multiplication unit is configured to multiply the data by the weights to provide multiplication results. The configurable summing unit is configured by Nth layer values to receive an Nth layer number of inputs and perform an Nth layer number of additions, and to sum the multiplication results and provide a configurable summing unit output.

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Abstract: A device includes a multiplication unit and a configurable summing unit. The multiplication unit is configured to receive data and weights for an Nth layer, where N is a positive integer. The multiplication unit is configured to multiply the data by the weights to provide multiplication results. The configurable summing unit is configured by Nth layer values to receive an Nth layer number of inputs and perform an Nth layer number of additions, and to sum the multiplication results and provide a configurable summing unit output.

Abstract: Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.

Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.

Abstract: A method for training an automatic driving model comprises: obtaining a sample acquisition strategy of the automatic driving model; transmitting the sample acquisition strategy of the automatic driving model to a vehicle equipment, the vehicle equipment being configured to sort objective driving data from a driving data set based on the sample acquisition strategy; receiving the objective driving data from the vehicle equipment; adding the objective driving data into a training set of the automatic driving model; and training the automatic driving model based on the training set. A system for training the automatic driving model is also disclosed.

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

Abstract: In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.

Abstract: A method for controlling a robot, a robot and a storage medium are provided by present application. The method includes determining a motion state of the robot based on preset information corresponding to the robot; in response that the motion state is in a non-balanced state, obtaining a motion plan corresponding to the balance-assistance assembly; controlling the motion state of the robot to change to the balanced state by controlling the balance-assistance assembly to move based on the motion plan. The method may improve balance performance of the robot.

Abstract: A method of generating an IC layout diagram includes generating a plurality of logic patterns, wherein each logic pattern corresponds to a number of bits N greater than two, arranging a column of NOR-type read-only memory (ROM) bit cells as a plurality of N-bit groups separated from each other by isolation features, assigning a pattern of the plurality of logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the plurality of logic patterns in a storage device.

Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.

Abstract: A method for identifying road vehicles or other objects which are in motion against those which are not moving applied in an in-vehicle device of an assisted vehicle which is being driven shoots a first image of a target vehicle and a second later image of the target vehicle, determines a first mask area of the target vehicle from the first image, and determines a second mask of the target vehicle from the second image based on an instance segmentation algorithm. An Intersection over Union (IoU) is calculated between the first mask area and the second mask area and a determination made as to whether a dynamic class object mask area of the target vehicle according to the IoU should be generated. A dynamic class object mask area of the target vehicle is generated when the target vehicle is found to be a moving vehicle.

Abstract: A driving assistance algorithm testing method applied to an electronic device is provided. In the method, the electronic device obtains a driving assistance algorithm to be tested of a vehicle and multiple specification parameters and models a virtual scene on a simulator according to the preset parameters and generates an initial image according to the virtual scene. The electronic device obtains a target image corresponding to the driving assistance algorithm by converting the initial image according to a preset sensor conversion algorithm and the specification parameters, and generates a target vehicle control instruction according to the driving assistance algorithm, the target image, a vehicle control conversion algorithm, and the specification parameters, and scores the driving assistance algorithm by executing the target vehicle control instruction in the virtual scene of the simulator. The method can improve a verification accuracy of the driving assistance algorithm.

Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface in contact with the channel layer. The first bottom surface underlaps the top surface of the gate structure across a first lateral direction. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along the first lateral direction, where the source structure has a second bottom surface facing the channel layer. The second bottom surface overlaps the top surface of the gate structure across the first lateral direction.

Abstract: A circuit includes a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first sense amplifier, a first bit line transistor, and a second bit line transistor. The first memory cell is coupled to the first bit line and the first word line. The second memory cell is coupled to the second bit line and the second word line. The first sense amplifier has a first terminal. The first bit line transistor selectively couples the first bit line to the first terminal of the first sense amplifier. The second bit line transistor selectively couples the second bit line to the first terminal of the first sense amplifier.

Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface facing the channel layer. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along a lateral direction, where the source structure has a second bottom surface facing the channel layer. The memory device includes a first channel pedestal and a second channel pedestals protruding from the channel layer.

Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

Abstract: The present disclosure describes a precharge circuit for a memory cell. In an example embodiment, a memory device comprises a memory array including a memory cell, a bit line connected to an output terminal of the memory cell, a reference bit line, and a sensing amplifier circuit coupled to the bit line and coupled to the reference bit line. The memory device further comprises a precharge circuit coupled to the bit line and the reference bit line.