Abstract: A memory device comprises a memory array, a plurality of access word lines, and a first tracking word line. The memory array may include a plurality of bit cells arranged over a plurality of rows and a plurality of columns. The plurality of access word lines may extend along a lateral direction. The plurality of rows may operatively correspond to the plurality of access word lines, respectively. The first tracking word line may also extend along the lateral direction and have a first portion extending from an edge of the memory array to a middle of the memory array and a second portion extending from the middle of the memory array to the edge of the memory array. The first combination can be different from the second combination.

Abstract: A method for identifying road vehicles or other objects which are in motion against those which are not moving applied in an in-vehicle device of an assisted vehicle which is being driven shoots a first image of a target vehicle and a second later image of the target vehicle, determines a first mask area of the target vehicle from the first image, and determines a second mask of the target vehicle from the second image based on an instance segmentation algorithm. An Intersection over Union (IoU) is calculated between the first mask area and the second mask area and a determination made as to whether a dynamic class object mask area of the target vehicle according to the IoU should be generated. A dynamic class object mask area of the target vehicle is generated when the target vehicle is found to be a moving vehicle.

Abstract: A driving assistance algorithm testing method applied to an electronic device is provided. In the method, the electronic device obtains a driving assistance algorithm to be tested of a vehicle and multiple specification parameters and models a virtual scene on a simulator according to the preset parameters and generates an initial image according to the virtual scene. The electronic device obtains a target image corresponding to the driving assistance algorithm by converting the initial image according to a preset sensor conversion algorithm and the specification parameters, and generates a target vehicle control instruction according to the driving assistance algorithm, the target image, a vehicle control conversion algorithm, and the specification parameters, and scores the driving assistance algorithm by executing the target vehicle control instruction in the virtual scene of the simulator. The method can improve a verification accuracy of the driving assistance algorithm.

Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface in contact with the channel layer. The first bottom surface underlaps the top surface of the gate structure across a first lateral direction. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along the first lateral direction, where the source structure has a second bottom surface facing the channel layer. The second bottom surface overlaps the top surface of the gate structure across the first lateral direction.

Abstract: A circuit includes a first bit line, a second bit line, a first word line, a second word line, a first memory cell, a second memory cell, a first sense amplifier, a first bit line transistor, and a second bit line transistor. The first memory cell is coupled to the first bit line and the first word line. The second memory cell is coupled to the second bit line and the second word line. The first sense amplifier has a first terminal. The first bit line transistor selectively couples the first bit line to the first terminal of the first sense amplifier. The second bit line transistor selectively couples the second bit line to the first terminal of the first sense amplifier.

Abstract: A memory device includes a channel layer. The memory device includes a gate structure on a first side of the channel layer, where the gate structure has a top surface facing the channel layer. The memory device includes a drain structure on a second side of the channel layer opposite to the first side, where the drain structure has a first bottom surface facing the channel layer. The memory device includes a source structure on the second side of the channel layer and adjacent to the drain structure along a lateral direction, where the source structure has a second bottom surface facing the channel layer. The memory device includes a first channel pedestal and a second channel pedestals protruding from the channel layer.

Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

Abstract: The present disclosure describes a precharge circuit for a memory cell. In an example embodiment, a memory device comprises a memory array including a memory cell, a bit line connected to an output terminal of the memory cell, a reference bit line, and a sensing amplifier circuit coupled to the bit line and coupled to the reference bit line. The memory device further comprises a precharge circuit coupled to the bit line and the reference bit line.

Abstract: A method for managing driving applied in an electronic device which assesses distances to objects in a path of autonomous driving obtains RGB images of a scene in front of a vehicle, processes the RGB images based on a trained depth estimation model, and obtain depth images corresponding to the RGB images. The depth images are converted to 3D point cloud maps, 3D regions of interest from the 3D point cloud maps are determined according to a size of the vehicle, and the 3D regions of interest are converted into 2D regions of interest according to internal parameters of a camera. The 2D regions of interest are analyzed for obstacles. Driving continues when the 2D regions of interest have no obstacles, the vehicle is controlled to issue an alarm when obstacles are discovered.

Abstract: The present invention relates to an artificial leather and a method for producing the same. The artificial leather includes a substrate, a thermoplastic ethylene-propylene polymer elastic layer, and a surface layer. The substrate is formed from fibers having a first thermoplastic ethylene-propylene polymer. The surface layer is formed from a second thermoplastic ethylene-propylene polymer. The first thermoplastic ethylene-propylene polymer and the second thermoplastic ethylene-propylene polymer provide the substrate with a specific melting point and the surface layer with a specific melting point, respectively. By the substrate with the specific melting point and the surface layer with the specific melting point, the artificial leather has an excellent post-processability. Therefore, the artificial leather can have the substrate and the surface layer which have the same material, thereby having an excellent recyclability.

Abstract: A computing device obtains a first image depicting a facial region of a user and an object occluding a portion of the facial region of the user. The computing device generates a second image of the user without the object occluding the portion of the facial region of the user based on the first image. A selection comprising desired eyeglasses is obtained, and the computing device generates a third image comprising the desired eyeglasses rendered on the second image to perform virtual try-on of the desired eyeglasses for the user to evaluate.

Abstract: An SRAM cell includes a first n-type channel (n-channel) layer engaged with a first gate layer to form a first device; a first p-type channel (p-channel) layer engaged with the first gate layer to form a second device, the first gate layer stacked between the first n-channel layer and the first p-channel layer along a first direction; a second n-channel layer engaged with a second gate layer to form a third device, the second gate layer coupled to a first word line and the second n-channel layer coupled to the first n-channel layer along a second direction perpendicular to the first direction; a third n-channel layer engaged with a third gate layer to form a fourth device, the third n-channel layer spaced from the second n-channel layer along a third direction perpendicular to the first direction and the second direction; a second p-channel layer engaged with the third gate layer to form a fifth device, the third gate layer stacked between the third n-channel layer and the second p-channel layer along the fir

Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.

Abstract: A semiconductor memory device includes a plurality of transistors disposed along a major surface of a substrate, a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate, and a plurality of memory cells formed within one or more of the metallization layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged with respect to each other along a vertical direction.

Abstract: The present disclosure relates to an step artificial leather having visual penetration and a manufacturing method thereof. The artificial leather includes a thermoplastic substrate, a thermoplastic adhering layer, and a thermoplastic surface layer. The thermoplastic substrate has fiber net shape, and has visual penetration. The thermoplastic adhering layer is disposed on the thermoplastic substrate. The thermoplastic surface layer is disposed on the thermoplastic adhering layer. The thermoplastic surface layer and the thermoplastic adhering layer are transparent. Therefore, the artificial leather of the present disclosure has visual penetration effect. The product made from the artificial leather of the present disclosure has attractive appearance and diversity.

Abstract: A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

Abstract: A method for controlling vehicles, an electronic device and a storage medium are provided. In the method, a license plate image of a target vehicle in front of a vehicle to be controlled and point cloud data of the target vehicle through a radar are acquired. The license plate image is identified to obtain initial vehicle data of the target vehicle. Target vehicle data of the target vehicle is calculated based on preset ranges, vehicle data of the vehicle to be controlled, the point cloud data and the initial vehicle data. In response that the target vehicle data meets preset conditions, the vehicle data of the vehicle to be controlled is adjusted according to the target vehicle data. The method can improve an accuracy of vehicle detection and a driving safety.

Abstract: A memory circuit includes a DRAM array oriented in a first plane, wherein the DRAM array includes a plurality of DRAM cells, a computation circuit oriented in a second plane parallel to the first plane and aligned with the DRAM array in a direction perpendicular to the first plane and the second plane, wherein the computation circuit includes a sense amplifier circuit, and a plurality of bit lines coupled to the plurality of DRAM cells and the sense amplifier circuit, wherein each bit line of the plurality of bit lines includes a via structure of a plurality of via structures extending in the direction between the first plane and the second plane. The plurality of DRAM cells of the DRAM array oriented in the first plane is an entirety of the DRAM cells of the memory circuit coupled to the sense amplifier circuit.

Abstract: A memory device including a memory array configured to store data, a senseamplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

Abstract: A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.