Abstract: The present disclosure provides an etching solution, including an ionic strength enhancer having an ionic strength greater than 10?3 M in the etching solution, wherein the ionic strength enhancer includes Li+, Na+, K+, Mg2+, Ca2+, N(CH3)+, or N(C2H5)4+, a solvent, and an etchant.

Abstract: Surgical teaching auxiliary system using virtual reality and method thereof are disclosed. In the Surgical teaching auxiliary system, virtual-reality surgical environment is created through three-dimensional reconstruction based on a two-dimensional surgical image, and an operation step, a time point of using instrument and a reference message are preset in advance; when a surgical training is performed in the virtual-reality surgical environment, a surgical operation behavior is continuously detected; when the surgical operation behavior abnormally interrupted or delayed is detected, an auxiliary support and guidance are triggered based on a progress of the surgical training, thereby achieving the technical effect of greatly improving the effectiveness of surgical learning in the virtual reality.

Abstract: Apparatus and methods are disclosed for using machine learning models with private and public domains. Operations can be applied to transform input to a machine learning model in a private domain that is kept secret or otherwise made unavailable to third parties. In one example of the disclosed technology, a method includes applying a private transform to produce transformed input, providing the transformed input to a machine learning model that was trained using a training set modified by the private transform, and generating inferences with the machine learning model using the transformed input. Examples of suitable transforms that can be employed include matrix multiplication, time or spatial domain to frequency domains, and partitioning a neural network model such that an input and at least one hidden layer form part of the private domain, while the remaining layers form part of the public domain.

Abstract: A surgical decision support system based on augmented reality (AR) and a method thereof are disclosed. In the surgical decision support system, a surgeon can create an optimal surgical operation before a surgical operation; during a surgical operation, the optimal surgical operation can be demonstrated through augmented reality, a current surgical operation is detected and compared with the optimal surgical operation, a difference message is displayed to provide a surgical decision support when a comparison difference exceeds a tolerable range. Therefore, the technical effect of improving operation efficiency and success rate can be achieved.

Abstract: Implementations of the subject matter described herein provide a solution for rate control based on reinforcement learning. In this solution, an encoding state of a video encoder is determined, the encoding state being associated with encoding of a first video unit by the video encoder. An encoding parameter associated with rate control in the video encoder is determined by a reinforcement learning model and based on the encoding state of the video encoder. A second video unit different from the first video unit is encoded based on the encoding parameter. In this way, it is possible to achieve a better quality of experience (QOE) for real time communication with computation overhead being reduced.

Abstract: The present disclosure provides an etching solution, including an ionic strength enhancer having an ionic strength greater than 10?3 M in the etching solution, wherein the ionic strength enhancer includes Li+, Na+, K+, Mg2+, Ca2+, N(CH3)+, or N(C2H5)4+, a solvent, and an etchant.

Abstract: Apparatus and methods are disclosed for using machine learning models with private and public domains. Operations can be applied to transform input to a machine learning model in a private domain that is kept secret or otherwise made unavailable to third parties. In one example of the disclosed technology, a method includes applying a private transform to produce transformed input, providing the transformed input to a machine learning model that was trained using a training set modified by the private transform, and generating inferences with the machine learning model using the transformed input. Examples of suitable transforms that can be employed include matrix multiplication, time or spatial domain to frequency domains, and partitioning a neural network model such that an input and at least one hidden layer form part of the private domain, while the remaining layers form part of the public domain.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

Abstract: A processor is provided with a register file comprising a plurality of vector registers, and an execution core coupled to the register file, where the execution core is configured to execute a set of checksum instructions with a first checksum instruction to specify a first vector operand, a second vector operand, and a result vector operand, where the first vector operand is in a first vector register of the plurality of vector registers, the second vector operand is in a second register of the plurality of vector registers, and the result vector operand is to be written to a third vector register of the plurality of vector registers, and to execute the first checksum instruction, the execution core is configured to accumulate bytes from the first vector operand and the second vector operand into a first portion of the result vector operand and add the accumulated bytes from the first vector operand and the second vector operand to a second portion of the result vector operand to generate the second portion

Abstract: An antenna structure applied in a wearable device includes a ceramic layer, a plastic layer, a radiating portion, a feed portion; and a connecting portion. The ceramic layer includes a first surface and a second surface corresponding to each other. The plastic layer is connected to the second surface. The radiating portion is a predetermined metal pattern and arranged in the first surface. The connecting portion passes through the plastic layer and is electrically connected to the feed portion. The feed portion feeds an electrical current to the radiating portion to generate radiation signals in at least one radiation frequency band. A wearable device having the antenna structure is also provided.

Abstract: An antenna structure applied in a wearable device includes a first radiating portion, a ceramic layer, a plastic layer, and a feed portion. The first radiating portion is a metal structure. The ceramic layer covers and contacts the first radiating portion. The first radiating portion is arranged between the ceramic layer and the plastic layer. The feed portion passes through the plastic layer and feeds an electric current into the first radiating portion, the first radiating portion and the ceramic layer cooperatively generate radiation signals in at least one radiation frequency band. A wearable device having the antenna structure is also provided.

Abstract: A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Abstract: A storage device management method for a storage device is provided. The method includes periodically obtaining a current device temperature corresponding to the storage device via a temperature sensor of the storage device; accumulating a first count value in response to determining that the current device temperature is greater than a first temperature threshold; adjusting the first temperature threshold in response to determining that the first count value is greater than the first count threshold; accumulating a second count value in response to determining that the current device temperature is greater than a second temperature threshold; adjusting the second temperature threshold in response to determining that the second count value is greater than the second count threshold; and controlling the storage device to enter a target system state in response to determining that the current device temperature is not less than a critical temperature threshold.

Abstract: A surgical procedure labeling and teaching system and a method thereof are disclosed. When one of names of to-be-labeled surgical images on a surgical image selection area of a user interface is selected, the to-be-labeled surgical image corresponding to the selected name is displayed on a surgical image labeling area of the user interface; after one of surgery label blocks on a surgery label selection area of the user interface is selected, a user can circle a surgery labeling area to establish a surgery feature label on the surgical image labeling area. A teaching interface can map the labeled surgical image to the to-be-labeled surgical image, so as to provide a surgical procedure teaching corresponding to the to-be-labeled surgical image. The technical effect of providing surgical procedure teaching by using the labeling-reference surgical image to assist in labeling and selecting of the to-be-labeled surgical image is achieved.

Abstract: A method for testing a memory chip includes: in response to read command for the memory chip, controlling clock signal to be kept in first state within first preset time period and at the same time controlling complementary clock signal to be kept in second state within first preset time period; in response to clock signal kept in the first state and complementary clock signal kept in the second state, keeping data strobe signal in the first state within second preset time period and at the same time keeping complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal and the complementary data strobe signal are kept in first and second states respectively, controlling first and second driving modules connected respectively to data strobe terminal and complementary data strobe terminal to operate and measure first and second resistance values respectively.

Abstract: Techniques are described for efficiently encoding video data by skipping evaluation of certain encoding modes based on various evaluation criteria. In some solutions, intra-block evaluation is performed in a specific order during encoding, and depending on encoding cost calculations of potential intra-block encoding modes, evaluation of some of the potential modes can be skipped. In some solutions, some encoding modes can be skipped depending on whether blocks are simple (e.g., simple vertical, simple horizontal, or both) or non-simple. In some solutions, various criteria are applied to determine whether chroma-from-luma mode evaluation can be skipped. The various solutions can be used independently and/or in combination.

Abstract: An attack path detection method, attack path detection system and non-transitory computer-readable medium are provided in this disclosure. The attack path detection method includes the following operations: establishing a connecting relationship among a plurality of hosts according to a host log set to generate a host association graph; labeling at least one host with an abnormal condition on the host association graph; calculating a risk value corresponding to each of the plurality of hosts; in a host without the abnormal condition, determining whether the risk value corresponding to the host without the abnormal condition is greater than a first threshold, and utilizing a host with the risk value greater than the first threshold as a high-risk host; and searching at least one host attach path from the high-risk host and the at least one host with the abnormal condition according to the connecting relationship of the host association graph.

Abstract: An electronic device selectively coupled to a first charger and/or a second charger includes a power supply interface, a first comparator, a second comparator, a controller, a first switch circuit, and a second switch circuit. The power supply interface receives a first input voltage and a second input voltage. The first comparator compares the first input voltage with a first reference voltage, so as to generate a first comparison voltage. The second comparator compares the second input voltage with a second reference voltage, so as to generate a second comparison voltage. The controller generates a first control voltage and a second control voltage according to the first comparison voltage and the second comparison voltage. The first switch circuit is selectively enabled or disabled according to the first control voltage. The second switch circuit is selectively enabled or disabled according to the second control voltage.

Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.