Patents by Inventor Chieh Lee
Chieh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948722Abstract: A planar winding transformer includes a magnetic core set and a multilayer circuit board. The magnetic core set includes two magnetic cores and two magnetic columns. The two magnetic cores are parallel to each other. The multilayer circuit board is disposed between two magnetic cores, and two magnetic columns penetrate through the multilayer circuit board. The multilayer circuit board includes two low voltage winding layers and one high voltage winding layer. Two low voltage winding layers are connected to each other in parallel, and the high voltage winding layer is disposed between two low voltage winding layers. When the high voltage winding layer receives a polarity current, at least one of the low voltage winding layers generates a corresponding induced current. Two magnetic cores and two magnetic columns form a closed path for magnetic flux.Type: GrantFiled: January 8, 2021Date of Patent: April 2, 2024Assignees: CHICONY POWER TECHNOLOGY CO., LTD., NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGYInventors: Yen-Shin Lai, Yong-Yi Huang, Chun-Hung Lee, Hao-Chieh Chang
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Patent number: 11950491Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.Type: GrantFiled: November 17, 2020Date of Patent: April 2, 2024Assignee: RAYNERGY TEK INCORPORATIONInventors: Yi-Ming Chang, Chuang-Yi Liao, Wei-Long Li, Yu-Tang Hsiao, Chun-Chieh Lee, Chia-Hua Li, Huei-Shuan Tan
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Patent number: 11949877Abstract: Innovations in adaptive encoding of screen content based on motion type are described. For example, a video encoder system receives a current picture of a video sequence. The video encoder system determines a current motion type for the video sequence and, based at least in part on the current motion type, sets one or more encoding parameters. Then, the video encoder system encodes the current picture according to the encoding parameter(s). The innovations can be used in real-time encoding scenarios when encoding screen content for a screen sharing application, desktop conferencing application, or other application. In some cases, the innovations allow a video encoder system to adapt compression to different characteristics of screen content at different times within the same video sequence.Type: GrantFiled: October 1, 2021Date of Patent: April 2, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Satya Sasikanth Bendapudi, Ming-Chieh Lee, Yan Lu, Bin Li, Jizhe Jin, Jiahao Li, Shao-Ting Wang
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Patent number: 11942364Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.Type: GrantFiled: July 20, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
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Patent number: 11943936Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.Type: GrantFiled: August 12, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
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Patent number: 11933817Abstract: A probe card device and a transmission structure are provided. The transmission structure includes a supporting layer, a plurality of metal conductors spaced apart from each other and slantingly inserted into the supporting layer, and an insulating resilient layer formed on the supporting layer. Each of the metal conductors includes a positioning segment held in the supporting layer, a connecting segment and an embedded segment respectively extending from two ends of the positioning segment, and an exposed segment extending from the embedded segment. Each of the embedded segments is embedded and fixed in the insulating resilient layer, and each of the exposed segments protrudes from the insulating resilient layer. When any one of the exposed segments is pressed by an external force, the insulating resilient layer is configured to absorb the external force through the corresponding embedded segment so as to have a deformation providing a stroke distance.Type: GrantFiled: January 13, 2022Date of Patent: March 19, 2024Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.Inventors: Wen-Tsung Lee, Hsun-Tai Wei, Pang-Chi Huang, Meng-Chieh Cheng
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Patent number: 11935890Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.Type: GrantFiled: April 11, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
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Patent number: 11936238Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.Type: GrantFiled: June 15, 2022Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Hsin-Chih Chen, Hung-Chieh Lin, Chao-Lung Kuo, Yi-Ping Hsieh, Chien-Shien Lee
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Publication number: 20240089620Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes two pixel arrays each having multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by a time ratio of the line time difference and the frame period. The TDI sensor doubles a number of times of integrating pixel data corresponding to the same position of a scene by arranging two separately operated pixel arrays.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: REN-CHIEH LIU, CHAO-CHI LEE
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Publication number: 20240088022Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
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Publication number: 20240079235Abstract: A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti -reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.Type: ApplicationFiled: November 2, 2023Publication date: March 7, 2024Inventors: Hung-Jui Kuo, Hsing-Chieh Lee, Ming-Tan Lee
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Publication number: 20240079524Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.Type: ApplicationFiled: September 6, 2023Publication date: March 7, 2024Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
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Patent number: 11918882Abstract: An interactive exercise apparatus for guiding a user to perform an exercise includes a display device and a detecting device. The display device is configured to display video imagery which shows an instructor image and at least one motion check image. The motion check image corresponds to a predetermined one of a plurality of body parts of the user, which has a motion guide track and a motion achievement evaluation. The detecting device is configured to detect displacement of the body parts. The motion guide track is displayed on a predetermined position of the video imagery with a predetermined track pattern, corresponding to a movement path of the predetermined body part when the user follows movements demonstrated by the instructor image to perform the exercise. The motion achievement evaluation indicates a matching degree determined according to the displacement of the predetermined body part detected by the detecting device.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: Johnson Health Tech Co., Ltd.Inventors: Hsin-Huang Chiang, Yu-Chieh Lee, Ning Chuang, Wei-Ting Weng, Cheng-Ho Yeh
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Patent number: 11923433Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.Type: GrantFiled: March 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
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Patent number: 11922578Abstract: A method for adjusting point cloud density, an electronic device, and a storage medium are provided. In the method an initial point cloud map and a distance determination threshold of a robot are obtained. A plurality of target regions in the initial point cloud map are determined, and an environmental complexity value of each target region is calculated. The initial point cloud map is divided into submaps, and a point cloud density coefficient of each submap is determined. The initial point cloud map is adjusted according to the point cloud density coefficient and the target point cloud map is obtained. By utilizing such method, adjustment efficiency and an accuracy of point cloud density can be improved.Type: GrantFiled: June 22, 2022Date of Patent: March 5, 2024Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jung-Yi Lin, Chieh Lee
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Patent number: 11923293Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.Type: GrantFiled: July 8, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
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Publication number: 20240073563Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Ren-Chieh LIU, Chao-Chi LEE, Yi-Yuan CHEN, En-Feng HSU
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Publication number: 20240071442Abstract: A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Chiao YEH, Chieh LEE, Chia-En HUANG, Ji Kuan LEE, Yao-Jen YANG
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Publication number: 20240071504Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE