Patents by Inventor Chieh-Te Chen

Chieh-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825818
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 3, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10818664
    Abstract: A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 27, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10784265
    Abstract: The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: September 22, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10734284
    Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
  • Publication number: 20200212042
    Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Publication number: 20200176453
    Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10658173
    Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
  • Patent number: 10658366
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Patent number: 10622362
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10593677
    Abstract: The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: March 17, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Ching Chang
  • Publication number: 20200083317
    Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
    Type: Application
    Filed: October 8, 2018
    Publication date: March 12, 2020
    Inventors: Kai-Lou Huang, Fu-Che Lee, Feng-Yi Chang, Chieh-Te Chen, Meng-Chia Tsai
  • Patent number: 10562762
    Abstract: A method of forming a semiconductor device includes following steps. First of all, plural first openings and plural second openings are sequentially formed on a material layer disposed on a substrate, with the second openings across the first openings to form plural overlapped regions. Then, plural patterns arranged in an array arrangement are formed, with each pattern overlapped each overlapped region, respectively. After that, transferring the first openings, the second openings and the patterns to the material layer, to from plural material patterns in an array arrangement. In another embodiment of the present invention, the first openings and the second openings may be replaced by plural first patterns and plural second patterns, while the patterns are replaced by plural openings.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 18, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10559651
    Abstract: The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 11, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Publication number: 20200020524
    Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 16, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
  • Patent number: 10490555
    Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: November 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Publication number: 20190341386
    Abstract: A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10446554
    Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: October 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Publication number: 20190304981
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10418367
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: September 17, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen