Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

Abstract: A patterning method is disclosed. A substrate having a hard mask layer and a first material layer formed thereon is provided. The first material layer is patterned into first array patterns and first peripheral patterns. The first array patterns are further transferred into first spacer patterns. Subsequently, a planarization layer and a second material layer are successively formed on the substrate. The second material layer is patterned into second array patterns and second peripheral patterns. The second array patterns are further transferred into second spacer patterns. The second spacer patterns partially overlap the first spacer patterns. The second peripheral patterns do not overlap the first peripheral pattern. The first spacer patterns not overlapped by the second spacer patterns are removed to obtain third array patterns. The hard mask layer is then etched using the third array patterns, the second peripheral patterns and the first peripheral patterns as an etching mask.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.

Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

Abstract: The present invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.

Abstract: A method for fabricating a pad structure includes the steps of: providing a material layer; forming an opening in the material layer; forming a conductive layer on the material layer and into the opening; forming a patterned mask on the conductive layer; performing a first etching process to remove part of the conductive layer for forming a conductive plug; and performing a shaping process to alter the shape of a top surface of the conductive plug.

Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

Abstract: A method of fabricating a mask includes providing a substrate. A first material layer is disposed on the substrate. Then, the first material layer is partly removed. A second trench is formed between the remaining first material layer. The second trench includes a height. Later, a second material layer is formed to conformally fill in the second trench. The second material layer includes a thickness. The thickness of the second material layer equals the height of the second trench. Finally, part of the second material layer is removed, and the remaining second material layer and the remaining first material layer comprise a second mask.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

Abstract: A method for fabricating a capacitor includes providing a substrate and a first etching stop layer on the substrate; forming a plurality of first spacers on the first etching stop layer; forming an organic layer and a second etching stop layer sequentially on the first spacers, the organic layer covering the first spacers; forming a plurality of second spacers on the second etching stop layer, each second spacer crossing the first spacers; transferring a pattern of the second spacers to the organic layer to form an organic pattern; performing an etching process using the organic pattern and the first spacers as a mask to form an etching stop pattern and remove the second etching stop layer; transferring the etching stop pattern to the substrate to form a plurality of through holes.

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.

Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.