Patents by Inventor Chieh-Te Chen
Chieh-Te Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140241027Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Po-Chao Tsao, Shu-Ru Wang, Chia-Wei Huang, Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang
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Patent number: 8785283Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.Type: GrantFiled: December 5, 2012Date of Patent: July 22, 2014Assignee: United Microelectronics Corp.Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
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Publication number: 20140151763Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao, Chieh-Te Chen
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Publication number: 20140154852Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
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Patent number: 8728949Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.Type: GrantFiled: August 9, 2010Date of Patent: May 20, 2014Assignee: United Microelectronics Corp.Inventors: Hung-Ling Shih, Shin-Chi Chen, Chieh-Te Chen, Wei-Hang Huang
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Publication number: 20140099760Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chieh-Te CHEN, Shih-Fang TZOU, Jiunn-Hsiung LIAO, Yi-Po LIN
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Patent number: 8691659Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.Type: GrantFiled: October 26, 2011Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Pin Hsu, Yi-Po Lin, Jiunn-Hsiung Liao, Chieh-Te Chen, Feng-Yi Chang, Shang-Yuan Tsai, Li-Chiang Chen
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Publication number: 20140073104Abstract: A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.Type: ApplicationFiled: September 10, 2012Publication date: March 13, 2014Inventors: Chieh-Te Chen, Yi-Po Lin, Jiunn-Hsiung Liao, Feng-Yi Chang, Shang-Yuan Tsai
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Patent number: 8633549Abstract: A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.Type: GrantFiled: October 6, 2011Date of Patent: January 21, 2014Assignee: United Microelectronics Corp.Inventors: Chieh-Te Chen, Shih-Fang Tzou, Jiunn-Hsiung Liao, Yi-Po Lin
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Publication number: 20130292775Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: ApplicationFiled: July 8, 2013Publication date: November 7, 2013Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Patent number: 8552503Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: GrantFiled: November 30, 2010Date of Patent: October 8, 2013Assignee: United Microelectronics Corp.Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Publication number: 20130200393Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Inventors: Chieh-Te Chen, Yi-Po Lin, Jiunn-Hsiung Liao, Shui-Yen Lu, Li-Chiang Chen
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Publication number: 20130109151Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Inventors: Ching-Pin Hsu, Yi-Po Lin, Jiunn-Hsiung Liao, Chieh-Te Chen, Feng-Yi Chang, Shang-Yuan Tsai, Li-Chiang Chen
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Publication number: 20130087861Abstract: A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chieh-Te CHEN, Shih-Fang Tzou, Jiunn-Hsiung Liao, Yi-Po Lin
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Publication number: 20130005151Abstract: In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.Type: ApplicationFiled: July 1, 2011Publication date: January 3, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chieh-Te CHEN, Yi-Po Lin, Feng-Yih Chang, Chih-Wen Feng, Shang-Yuan Tsai
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Publication number: 20120132996Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Inventors: Guang-Yaw Hwang, Ling-Chun Chou, I-Chang Wang, Shin-Chuan Huang, Jiunn-Hsiung Liao, Shin-Chi Chen, Pau-Chung Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chieh-Te Chen
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Publication number: 20120034780Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.Type: ApplicationFiled: August 9, 2010Publication date: February 9, 2012Inventors: Hung-Ling Shih, Shin-Chi Chen, Chieh-Te Chen, Wei-Hang Huang
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Patent number: 8026571Abstract: A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids.Type: GrantFiled: May 29, 2008Date of Patent: September 27, 2011Assignee: United Microelectronics Corp.Inventors: Shui-Yen Lu, Guang-Wei Ye, Shin-Chi Chen, Tsung-Wen Chen, Ching-Fang Chu, Chi-Horn Pai, Chieh-Te Chen
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Publication number: 20100213554Abstract: A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Inventors: I-Chang Wang, Ming-Tsung Chen, Ling-Chun Chou, Po-Chao Tsao, Tsung-Hung Chang, Hui-Ling Chen, Cheng-Yen Wu, Chieh-Te Chen, Shin-Chi Chen
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Publication number: 20100188241Abstract: The present invention discloses a current detection and precaution alarm device consisting of a current sensing device, a current voltage converter, an alarm device, a selection adjusting button and an illumination device, and primarily used in a current loop of an electric power system for detecting a current signal of the current loop without changing any original power circuit of the electric power system or preparing an operating power supply. If the detected current quantity exceeds a default setting, sound and light alarm signals will be generated to remind users to reduce the power consumption and prevent a possible risk or a sudden power failure caused by a current overload, so as to improve the practical value and electric safety of a product.Type: ApplicationFiled: January 23, 2009Publication date: July 29, 2010Inventor: Chieh-Te Chen