Patents by Inventor Chien-An Lai

Chien-An Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12315562
    Abstract: A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.
    Type: Grant
    Filed: June 14, 2024
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
  • Publication number: 20250112460
    Abstract: A power supply includes a conversion circuit, an auxiliary power circuit, and an output control circuit. The conversion circuit converts a DC power into a first output power, and the auxiliary power circuit converts the DC power into a first auxiliary power. The output control circuit is used to selectively connect a first output terminal and a second output terminal so that when the output control circuit disconnects the first output terminal and the second output terminal, the first output power supplies power to a critical load through the first output terminal, and when the output control circuit connects the first output terminal and the second output terminal, the first output power supplies power to the critical load and a non-critical load through the first output terminal and the second output terminal respectively.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 3, 2025
    Inventors: Cheng-Chan HSU, Chien-An LAI, Guo-Ning CHEN, Yung-Yuan HSIAO, Kai-Lin CHANG
  • Publication number: 20250112471
    Abstract: A power supply equipment supplies power to a critical load and a non-critical load. The power supply equipment includes a plurality of power supplies coupled in parallel and a system controller. The system controller is coupled to the power supplies, and communicates with the power supplies to set a specific sequence. The system controller notifies the power supplies to adjust operating frequencies to be inconsistent according to the specific sequence.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 3, 2025
    Inventors: Chien-An LAI, Guo-Ning CHEN, Yung-Yuan HSIAO
  • Publication number: 20250023277
    Abstract: The present disclosure provides an electrical connection assembly including a first electrical connector and a second electrical connector. The first electrical connector includes a first terminal. The first terminal includes a contact part. The second electrical connector is configured to pluggably connect with the first electrical connector, and includes a second terminal. The second terminal includes a recess. The recess is inwardly recessed from a surface of the second terminal and includes a connection section and a bottom. The connection section is in connection between the bottom and the surface of the second terminal, and includes a plurality of contact portions. The contact part of the first terminal is in connection with the recess of the second terminal, and the contact part of the first terminal is in contact with the bottom and the contact portions of the recess of the second terminal to form a multi-points contact.
    Type: Application
    Filed: July 12, 2024
    Publication date: January 16, 2025
    Inventors: Chien-An Lai, Yu-Tai Wang, Hao-Peng Cheng, I Chen
  • Publication number: 20240429809
    Abstract: A power supply apparatus includes a power factor correction circuit, an LLC converter, an auxiliary conversion circuit, a secondary side controller and a voltage tracking circuit. The power factor correction circuit is used for converting a DC link voltage into a first voltage. The LLC converter includes a primary side circuit and a secondary side circuit, which are coupled with each other. The primary side circuit receives the first voltage. The first voltage is converted into an auxiliary voltage by the auxiliary conversion circuit. The voltage tracking circuit detects the auxiliary voltage and issues a detection signal to the secondary side controller. The secondary side controller tracks a ripple change of the DC link voltage and instantly generates a reverse waveform opposite to a waveform of the DC link voltage. The secondary side controller controls the operations of the LLC converter according to the reverse waveform.
    Type: Application
    Filed: May 6, 2024
    Publication date: December 26, 2024
    Inventors: Chien-An Lai, I Chen
  • Publication number: 20240429817
    Abstract: A power supply unit includes an input terminal, an output terminal, a main circuit, an ORing field effect transistor, a driving circuit and a switch. The main circuit is connected between the input terminal and the output terminal. The ORing field effect transistor is connected between the output terminal and the main circuit. The driving circuit is connected with a control terminal of the ORing field effect transistor. The driving circuit generates a control signal to control the ORing field effect transistor. The switch is connected between the driving circuit and the control terminal of the ORing field effect transistor. Before the power supply unit is plugged into a system bus of a power supply system, the control signal from the driving circuit is bypassed by the switch. Consequently, the ORing field effect transistor is turned off.
    Type: Application
    Filed: May 8, 2024
    Publication date: December 26, 2024
    Inventors: Chien-An Lai, Lin-Ya Tsai, Chang-Yuan Hsu
  • Publication number: 20240331770
    Abstract: A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
  • Publication number: 20240322701
    Abstract: A synchronous rectification control method for a resonant power supply includes steps as follows. First, setting an initial conduction width of a synchronous rectification switch, which is less than a maximum conduction width. Afterward, detecting a voltage waveform across two ends of a body diode of the synchronous rectification switch. Afterward, calculating a resonant frequency according to the voltage waveform. Finally, determining the maximum conduction width of the synchronous rectification switch.
    Type: Application
    Filed: June 26, 2023
    Publication date: September 26, 2024
    Inventors: Lin-Ya TSAI, Chien-An LAI
  • Patent number: 12014776
    Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Publication number: 20240161969
    Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, an inductor iron core, and a current transformer trace. The inductor trace is arranged on the primary-side circuit and formed one layer board of the circuit board to serve as a resonant inductor coupled to the primary-side circuit. The inductor iron core includes a core pillar, and the core pillar penetrates a through hole of the circuit board, and the inductor trace surrounds the through hole. The current transformer trace is formed on the circuit board to serve as a current transformer coil coupled to the resonant inductor. The current transformer trace surrounds the through hole to form a common-core structure that shares the inductor iron core.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsun CHIU, Yi-Sheng CHANG, Chien-An LAI, Chia-Wei CHU
  • Publication number: 20240161966
    Abstract: A planar magnetic component is arranged on a circuit board of a resonant converter, and the resonant converter includes a primary-side circuit and a secondary-side circuit. The planar magnetic component includes an inductor trace, a primary-side trace, a secondary-side trace, and an iron core assembly. The iron core assembly includes an inductor iron core and an iron core. The primary-side trace surrounds the first through hole in a first direction and surrounds the second through hole in a second direction to form an ?-shaped trace. The inductor trace is formed on the primary-side layer board and coupled to the primary-side trace, and two ends of the inductor trace form an input terminal and an output terminal of the planar magnetic component.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Chien-An LAI, Yi-Hsun CHIU, Chun-Yu YANG
  • Publication number: 20230402075
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 14, 2023
    Inventors: CHIEN-AN LAI, CHUNG-CHENG CHOU, YU-DER CHIH
  • Patent number: 11735238
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11545891
    Abstract: A power device includes a power factor corrector, an auxiliary capacitor, a switching device, an auxiliary boost circuit, a controller and a voltage conversion device. The switching device has a first end electrically connected to the output end of the power factor corrector, and a second end electrically connected to one end of the auxiliary capacitor. An output end of the auxiliary boost circuit is electrically connected to the output end of the power factor corrector, an input end of the auxiliary boost circuit is electrically connected to a middle end of the switching device, and a ground end of the auxiliary boost circuit is electrically connected to another end of the auxiliary capacitor. The controller is electrically connected to the switching device and the auxiliary boost circuit. The input end of the voltage conversion device is electrically connected to the output end of the power factor corrector.
    Type: Grant
    Filed: August 8, 2021
    Date of Patent: January 3, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-An Lai, Jyun-Jhe Jhang, Chien-Yao Liao, Ping-Sheng Wu, I Chen, Chang-Yuan Hsu
  • Publication number: 20220336016
    Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
  • Publication number: 20220335996
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: CHIEN-AN LAI, CHUNG-CHENG CHOU, YU-DER CHIH
  • Publication number: 20220238155
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 11393528
    Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Chien-An Lai, Hsu-Shun Chen, Zheng-Jun Lin, Pei-Ling Tseng
  • Patent number: 11393512
    Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih