Abstract: A lighting module, an electronic device, and a display panel are provided. The lighting module includes a carrier, a first metal circuit layer, a first transparent conductive layer, a first insulating layer, a second transparent conductive layer, a second metal circuit layer, a bonding structure layer, and a plurality of lighting units. The bonding structure layer is configured to allow the second metal circuit layer to be well bonded to the first insulating layer, so that a resistance value of the lighting module is decreased, and a pressure drop is reduced.

Abstract: An electronic device includes a first body including a first part and a second part hinged to each other, a second body, and a hinge structure hinged between an edge of the second body and the second part. The first part has a recess. When the second body is unfolded relative to the first body from a folded state to a first unfolded state, the hinge structure pushes against the first part to rotate the first part relative to the second part. When the second body is continuously unfolded relative to the first body from the first unfolded state to a second unfolded state, the edge of the second body pushes against the first part, so that the first part continues to rotate relative to the second part. When the second body is in the folded state, the hinge structure is at least partially accommodated in the recess.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: An electronic device with movable foot pad, including a body and a foot pad module, is provided. The body has a bottom surface. The foot pad module includes a first foot pad, at least one second foot pad, and at least one rotating shaft connecting the first and second foot pads. The second foot pad is rotated relative to the first foot pad by the rotating shaft to switch the foot pad module between first and second states. An axial direction of the rotating shaft is inclined relative to the bottom surface. In the first state, the body is supported on the platform by the first and second foot pads. In the second state, the second foot pad is rotated 180 degrees relative to the first foot pad in the axial direction and protrudes from the first foot pad to support the body on the platform by the second foot pad.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: A consumable component of an injecting physiological monitor includes a housing, an injecting module, a physiological monitor, and a carrier. The injecting module is movably assembled on the housing. The physiological monitor is disposed in the housing and located on a movement path of the injecting module. A part of a structure of the physiological monitor is accommodated in a part of a structure of the injecting module. The carrier is disposed in the housing and located on a movement path of the injecting module and the physiological monitor. The carrier and the physiological monitor are separated from each other and located on opposite sides of the housing. The housing and the injecting module are adapted to be assembled to an injector. The injector is adapted to drive the physiological monitor to be assembled to the carrier through the injecting module.

Abstract: An electronic device includes a first body including a first part and a second part hinged to each other, a second body, and a hinge structure hinged between an edge of the second body and the second part. The first part has a recess. When the second body is unfolded relative to the first body from a folded state to a first unfolded state, the hinge structure pushes against the first part to rotate the first part relative to the second part. When the second body is continuously unfolded relative to the first body from the first unfolded state to a second unfolded state, the edge of the second body pushes against the first part, so that the first part continues to rotate relative to the second part. When the second body is in the folded state, the hinge structure is at least partially accommodated in the recess.

Abstract: A method for curing antenna violations on an integrated circuit that includes multiple levels includes: obtaining a design of a circuit, the design including a first element connected to first device and a second element connected to one or more second devices, wherein the first and second elements both receive a common signal; determining that an antenna violation exists in on the first element at a first level of the multiple levels; and modifying the design of the circuit to add a connected between the first element and the second element at the first layer or at a layer below the first layer.

Abstract: A power device includes a power factor corrector, an auxiliary capacitor, a switching device, an auxiliary boost circuit, a controller and a voltage conversion device. The switching device has a first end electrically connected to the output end of the power factor corrector, and a second end electrically connected to one end of the auxiliary capacitor. An output end of the auxiliary boost circuit is electrically connected to the output end of the power factor corrector, an input end of the auxiliary boost circuit is electrically connected to a middle end of the switching device, and a ground end of the auxiliary boost circuit is electrically connected to another end of the auxiliary capacitor. The controller is electrically connected to the switching device and the auxiliary boost circuit. The input end of the voltage conversion device is electrically connected to the output end of the power factor corrector.

Abstract: Embodiments of the invention include protecting against antenna violations in a macro having a clock mesh. Aspects include obtaining a design of the macro, the design including a clock layer having a plurality of clock pins and determining a longest vertical wire and a longest horizontal wire allowed based on a design of the clock mesh. Aspects also include identifying, based at least in part on the longest vertical wire and the longest horizontal wire, a plurality of checkbox regions for a clock pin of the plurality of clock pins and calculating a total diffusion area for each of the plurality of checkbox regions. Aspects further include adding, to the design of the macro, an antenna diode to the clock pin based on a determination that the total diffusion area for any of the plurality of checkbox regions is less than a threshold value.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.

Abstract: A power device includes a power factor corrector, an auxiliary capacitor, a switching device, an auxiliary boost circuit, a controller and a voltage conversion device. The switching device has a first end electrically connected to the output end of the power factor corrector, and a second end electrically connected to one end of the auxiliary capacitor. An output end of the auxiliary boost circuit is electrically connected to the output end of the power factor corrector, an input end of the auxiliary boost circuit is electrically connected to a middle end of the switching device, and a ground end of the auxiliary boost circuit is electrically connected to another end of the auxiliary capacitor. The controller is electrically connected to the switching device and the auxiliary boost circuit. The input end of the voltage conversion device is electrically connected to the output end of the power factor corrector.

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

Abstract: A surge current suppression circuit includes a switch, a bypass resistor, a detection resistor, and a comparator. The switch is coupled to a first end of an energy storage capacitor in series, wherein a second end of the energy storage capacitor is coupled to a load and receives an input power source. The bypass resistor is coupled to the switch in parallel. The detection resistor is coupled to the switch in series to generate a detection voltage according to a capacitor current flowing through the energy storage capacitor. The comparator compares the detection voltage with a reference voltage to generate a control signal. When the detection voltage is greater than the reference voltage, the control signal controls the switch to be turned off. When the detection voltage is less than the reference voltage, the control signal controls the main switch to be turned on.

Abstract: An active bridge rectifier circuit includes a rectifier unit and a control unit. The rectifier unit includes a first upper bridge switch, a second upper bridge switch, a first lower bridge switch, and a second lower bridge switch. The control unit includes a first signal comparator and a second signal comparator. The first signal comparator compares a live wire signal provided from a live wire end with a neutral wire signal provided from a neutral wire end to generate a first comparison signal. The second signal comparator compares the live wire signal with the neutral wire signal to generate a second comparison signal. The first comparison signal controls the first upper bridge switch and the first lower bridge switch. The second comparison signal controls the second upper bridge switch and the second lower bridge switch.

Abstract: A surge current suppression circuit includes a switch, a bypass resistor, a detection resistor, and a comparator. The switch is coupled to a first end of an energy storage capacitor in series, wherein a second end of the energy storage capacitor is coupled to a load and receives an input power source. The bypass resistor is coupled to the switch in parallel. The detection resistor is coupled to the switch in series to generate a detection voltage according to a capacitor current flowing through the energy storage capacitor. The comparator compares the detection voltage with a reference voltage to generate a control signal. When the detection voltage is greater than the reference voltage, the control signal controls the switch to be turned off. When the detection voltage is less than the reference voltage, the control signal controls the main switch to be turned on.