Patents by Inventor Chien-Chang Lin
Chien-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240304561Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: ApplicationFiled: May 14, 2024Publication date: September 12, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Publication number: 20240274632Abstract: A semiconductor device includes a plurality of photodiodes, a semiconductor structure, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor structure overlaps the photodiodes. The semiconductor structure includes a plurality of microstructures on a backside of the semiconductor structure. The dielectric layer is over the microstructures of the semiconductor structure. A thickness of the dielectric layer is less than a vertical distance from one of the photodiodes to one of the microstructures. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.Type: ApplicationFiled: April 25, 2024Publication date: August 15, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Nan TU, Yu-Lung YEH, Hsing-Chih LIN, Chien-Chang HUANG, Shih-Shiung CHEN
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Patent number: 12051736Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.Type: GrantFiled: August 31, 2021Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12048944Abstract: A method of preventing drippage in a fluid dispensing system. The fluid dispensing system includes a first automatic control valve (ACV), an input of the first ACV connected to fluid-source of fluid, the first ACV having positions ranging from fully closed to fully open, and a second ACV, an input of the second ACV being connected to an output of the first ACV, and an output of the second ACV being connected to a nozzle, the second ACV having positions ranging from fully closed to fully open. The method includes generating a first proxy signal representing at least a first indirect measure of a position of the first ACV. The method includes recognizing, based on at least the first proxy signal that a failure state exists in which the first ACV has failed to close. The method includes causing the second ACV to close when the failure state exists.Type: GrantFiled: October 5, 2020Date of Patent: July 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hung Wang, Chun-Chih Lin, Chi-Hung Liao, Yung-Yao Lee, Wei Chang Cheng
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Patent number: 12014992Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: GrantFiled: November 9, 2022Date of Patent: June 18, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
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Publication number: 20230307385Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: ApplicationFiled: May 30, 2023Publication date: September 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
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Publication number: 20230283905Abstract: An image capturing assembly including a mounting base, a driving component, a first gear, a second gear, a lens assembly, a third gear and a resistance component. The driving component is disposed on the mounting base. The first gear is connected to the driving component and configured to be driven by the driving component. The second gear is pivotally connected to the mounting base and connected to the first gear. The driving component is configured to drive the second gear via the first gear. The lens assembly is fixed to the second gear. The third gear is pivotally connected to the mounting base and engaged with the second gear. The resistance component presses against the third gear to allow the third gear to transmit a resistance against the second gear during a rotation of the second gear.Type: ApplicationFiled: March 1, 2023Publication date: September 7, 2023Applicant: AVER INFORMATION INC.Inventors: Ming-Te CHENG, Chien-Chang LIN
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Patent number: 11705408Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: GrantFiled: February 25, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
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Publication number: 20230061943Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: ApplicationFiled: November 9, 2022Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Patent number: 11574857Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.Type: GrantFiled: March 23, 2020Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Chien-Chang Lin
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Publication number: 20230029269Abstract: An apparatus for collecting information communicating with a server and a collecting device includes scanning a bar code and transmit identification information of the apparatus to the server; the bar code is configured to link to a webpage of the server; acquiring biological characteristic information of a user of the apparatus collected by the collecting device; acquiring the identification information and the biological characteristic information matched by the server; and displaying the identification information and the biological characteristic information synchronized with the server. A method and a server for collecting information are also disclosed.Type: ApplicationFiled: July 22, 2021Publication date: January 26, 2023Inventor: Chien-Chang LIN
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Patent number: 11508666Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: GrantFiled: June 29, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Publication number: 20220270987Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
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Publication number: 20210407914Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
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Publication number: 20210296221Abstract: A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Chien-Chang Lin
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Patent number: 11018113Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.Type: GrantFiled: October 17, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lipu Kris Chuang, Chung-Hao Tsai, Hsin-Yu Pan, Yi-Che Chiang, Chien-Chang Lin
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Publication number: 20210118847Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lipu Kris Chuang, Chung-Hao Tsai, Hsin-Yu Pan, Yi-Che Chiang, Chien-Chang Lin
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Publication number: 20200329085Abstract: A real-time video notification method for a transportation vehicle is executed by a real-time video notification system, and the real-time video notification method includes steps of: pairing an electronic device with a cloud server; capturing in-transportation-vehicle images; and transmitting the real-time video information and the position signal to the cloud server. The real-time video notification system includes a cloud server and an electronic device, wirelessly communicating with the cloud server. The electronic device includes a central processing unit (CPU), electrically connected to a camera module, a position module, an emergency button, and a wireless transmission circuit. The real-time video notification method and the real-time video notification system facilitate a driver or a passenger to seek help on their own as soon as possible in case of emergency.Type: ApplicationFiled: April 9, 2019Publication date: October 15, 2020Applicant: RIGO GLOBAL CO., LTD.Inventor: Chien-Chang LIN
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Patent number: 10672681Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.Type: GrantFiled: April 30, 2018Date of Patent: June 2, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chang Lin, Hsin-Yu Pan, Lipu Kris Chuang, Ming-Chang Lu