Patents by Inventor Chien Cheng Chen

Chien Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11029593
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Patent number: 11020594
    Abstract: The invention relates to an electrochemical dephosphorylation technique for treating Alzheimer's disease and a use thereof. It comprises a gold electrode provided with a negative potential of ?0.2 V to ?0.6 V on a surface thereof.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 1, 2021
    Assignee: National Chiao Tung University
    Inventors: Jung-Chih Chen, I-Chiu Li, Kun-Che Li, Ching-Cheng Chuang, Mei-Lan Ko, Hsin-Yu Chen, Chia-Hsuan Chang, Hsin-Yi Tsai, Chien-Chih Hsu
  • Patent number: 11003082
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and providing a resist solution. The resist solution includes a plurality of first polymers and a plurality of second polymers, each of the first polymers includes a first polymer backbone, and a first acid-labile group (ALG) with a first activation energy bonded to the first polymer backbone. Each of the second polymers includes a second polymer backbone, and a second acid-labile group with a second activation energy bonded to the second polymer backbone, the second activation energy is greater than the first activation energy. The method includes forming a resist layer over the material layer, and the resist layer includes a top portion and a bottom portion, and the first polymers diffuse to the bottom portion, and the second polymers diffuse to the top portion.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chih Chen, Yahru Cheng, Ching-Yu Chang
  • Patent number: 11002704
    Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
  • Publication number: 20210125885
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 10991422
    Abstract: High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: April 27, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Ting Huang, Liang-Cheng Chen
  • Patent number: 10990744
    Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Huang, Bo-Han Chen, Cherng-Shyan Tsay, Chien Wen Lai, Hua-Tai Lin, Chia-Cheng Chang, Lun-Wen Yeh, Shun-Shing Yang
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 10893608
    Abstract: The present invention provides a fabric having a multiple layered circuit thereon integrating with electronic devices. The fabric comprises: a base layer; a plurality of conductive circuit layers; at least one connecting layer having electrically-conductive via-hole(s) and electrically-insulated area covering the area without the via-hole(s) and electrically connecting two conductive circuit layers through the via-hole(s) but electrically insulating the rest of the two conductive circuit layers; one or more than one electrical devices mounted to the conductive circuit layer and connected to circuits on the conductive circuit layer through anisotropic conductive film (ACF); and a water-proof layer disposed on the conductive circuit layer which is the farthest away from the base layer and covering the electrical device(s).
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: January 12, 2021
    Assignee: National Taipei University of Technology
    Inventors: Tzu-Wei Chou, Syang-Peng Rwei, Chien-Cheng Chen, Guo-Ming Sung
  • Patent number: 10866504
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Patent number: 10772509
    Abstract: A method for determining emptying of upper gastrointestinal tract includes the steps of: providing an upper gastrointestinal monitoring system including a detecting device, a transmission module, a signal processing device and a signal display; acquiring a time signal of RGB three primary colors of an upper gastrointestinal tract image with the detecting device; transmitting the time signal of RGB three primary colors by the transmission module to the signal processing device; calculating an intensity ratio of the time signal of RGB three primary color; evaluating the upper gastrointestinal emptying according to the intensity ratio of the time signal of RGB three primary color; and displaying the evaluation result on the signal display.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 15, 2020
    Assignee: MEDIVISIONTECH CO., LTD.
    Inventors: Chien-Cheng Chen, Chiao-Hsiung Chuang
  • Patent number: 10772508
    Abstract: A method for determining upper gastrointestinal bleeding course includes the steps of: providing an upper gastrointestinal bleeding monitoring system including a bleeding detecting device, a transmission module, a signal processing device and a signal display; acquiring a time signal of RGB three primary colors of an upper gastrointestinal tract image with the bleeding detecting device; transmitting the time signal of RGB three primary colors by the transmission module to the signal processing device; calculating an intensity ratio of the time signal of RGB three primary color; evaluating the upper gastrointestinal bleeding course according to the intensity ratio of the time signal of RGB three primary color; and displaying the evaluation result on the signal display.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 15, 2020
    Assignee: MEDIVISIONTECH CO., LTD.
    Inventors: Chien-Cheng Chen, Chiao-Hsiung Chuang
  • Publication number: 20200268540
    Abstract: A knee-supporting assembly has a supporting device and two belt frames. The supporting device has a securing board assembly, two wheels, a driving axle, an operating member, a transmission assembly, and a pushing member. The wheels are mounted rotatably on the securing board assembly. The driving axle is connected eccentrically with the two wheels. The operating member is connected securely to the driving axle. The transmission assembly is connected with and driven by the driving axle to be reciprocatively moveable relative to the securing board assembly and has a first end connected with the driving axle and a second end. The pushing member is connected with the second end of the transmission assembly. The belt frames are connected respectively with two ends of the securing board assembly.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Inventor: Chien-Cheng CHEN
  • Publication number: 20200098545
    Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
  • Publication number: 20200050098
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Publication number: 20190196322
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Publication number: 20190150760
    Abstract: A method for determining emptying of upper gastrointestinal tract includes the steps of: providing an upper gastrointestinal monitoring system including a detecting device, a transmission module, a signal processing device and a signal display; acquiring a time signal of RGB three primary colors of an upper gastrointestinal tract image with the detecting device; transmitting the time signal of RGB three primary colors by the transmission module to the signal processing device; calculating an intensity ratio of the time signal of RGB three primary color; evaluating the upper gastrointestinal emptying according to the intensity ratio of the time signal of RGB three primary color; and displaying the evaluation result on the signal display.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 23, 2019
    Inventors: Chien-Cheng Chen, Chiao-Hsiung Chuang
  • Patent number: D912661
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 9, 2021
    Assignee: Dell Products L.P.
    Inventors: Eid-Beng Goh, Chih Chieh Chang, An-Chung Hsieh, Chien-Cheng Chen, Kyu Sang Park