Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.

Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Abstract: A display device including a substrate, a cholesteric liquid crystal layer, and a transparent electrode layer that are sequentially stacked is provided. The cholesteric liquid crystal layer includes cholesteric liquid crystal molecules and a plurality of transparent photoresist structures. Each of the transparent photoresist structures is a closed structure, and the cholesteric liquid crystal molecules are respectively accommodated in a plurality of patterned areas respectively surrounded by the transparent photoresist structures, so as to form a plurality of cholesteric liquid crystal patterns. The transparent electrode layer includes a plurality of sub-electrodes. The cholesteric liquid crystal patterns are respectively driven by the sub-electrodes. An orthogonal projection of each of the transparent photoresist structures on the substrate falls in an orthogonal projection of a corresponding sub-electrode of the sub-electrodes on the substrate.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.

Abstract: An atomization module includes a main fixing member, an auxiliary fixing member, an atomization component and a piezoelectric component. The main fixing member includes a first bonding part, a second bonding part and a connecting part. The first bonding part has a first opening and a first bonding surface surrounding the first opening. The second bonding part is connected to the first bonding part, and the connecting part and the second bonding part surround the first bonding part. The auxiliary fixing member has a second opening and a second bonding surface surrounding the second opening. The piezoelectric component surrounds the first bonding part. The main fixing member has a first adhesive groove, which is jointly defined at least by the main fixing member, the auxiliary fixing member and the atomization component. The first adhesive is provided in the first adhesive groove.

Abstract: A package structure, including: a first packaging member having oppositely arranged first surface and second surface; a control chip covered by the first packaging member; a plurality of conductors provided on and protruding from the control chip and electrically connected to electrical contacts of the control chip, the conductors being covered by the first packaging member, and ends of the conductors facing away from the control chip being flush with the first surface; a wire pattern layer disposed on the first surface and electrically connected to the conductors; a light emitting element located on the first surface and electrically connected to the control chip via the wire pattern layer; and a second packaging member covering the light emitting element and affixed to the first surface and the wire pattern layer, a light beam emitted by the light emitting element being allowed to travel outward through the second packaging member.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.

Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

Abstract: Provided are apparatus and systems for performing a swing adsorption process. In particular, the method and system involves swing adsorption processes and systems designed to lessen the temperature, pressure and product stream composition fluctuations in the adsorption step of a swing adsorption process, particularly involving preparation of the adsorption bed unit using feed stream cooling in conjunction with splitting the cooled feed stream to the adsorption bed units during adsorption steps while staggering the timing of back-to-back adsorption steps in the swing adsorption process. The process may be utilized for swing adsorption processes, such as rapid cycle TSA and/or rapid cycle PSA, which are utilized to remove one or more contaminants from a gaseous feed stream.