Patents by Inventor Chien-Chung Huang

Chien-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105887
    Abstract: A package structure, including: a first packaging member having oppositely arranged first surface and second surface; a control chip covered by the first packaging member; a plurality of conductors provided on and protruding from the control chip and electrically connected to electrical contacts of the control chip, the conductors being covered by the first packaging member, and ends of the conductors facing away from the control chip being flush with the first surface; a wire pattern layer disposed on the first surface and electrically connected to the conductors; a light emitting element located on the first surface and electrically connected to the control chip via the wire pattern layer; and a second packaging member covering the light emitting element and affixed to the first surface and the wire pattern layer, a light beam emitted by the light emitting element being allowed to travel outward through the second packaging member.
    Type: Application
    Filed: April 14, 2023
    Publication date: March 28, 2024
    Inventors: Chih-Hung TZENG, Chih-Chiang KAO, Chien-Chung HUANG
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11944017
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240096929
    Abstract: A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yan-Jhih HUANG, Chun-Yuan HSU, Chien-Chung CHEN, Yung-Hsieh LIN
  • Patent number: 11898032
    Abstract: Disclosed is a biodegradable composition, including: 5 to 90 percent by weight of polylactic acid (PLA), 5 to 80 percent by weight of plant fiber, and 5 to 70 percent by weight of maleic anhydride-grafted polybutylene succinate (PBS-g-MA), acrylic acid-grafted polybutylene succinate (PBS-g-AA), or silane coupling agent-grafted polybutylene succinate (PBS-g-Silane). The article manufactured therefrom is not only biodegradable but also has an enhanced heat deformation temperature, impact resistance and tensile strength. Further, by so limiting the proportion of each component, compatibility between the components may be increased and crystallization of polylactic acid may be facilitated.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 13, 2024
    Inventor: Chien-Chung Huang
  • Publication number: 20240023457
    Abstract: An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Patent number: 11856865
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20230407096
    Abstract: A biodegradable straw, which includes: a plant acid-modified plant fiber material, accounting for 20 wt % to 70 wt % of a total weight of the biodegradable straw; and a PBS material, accounting for 30 wt % to 80 wt % of the total weight of the biodegradable straw; wherein the plant acid-modified plant fiber material is mixed with the PBS material and then extruded and molded into the biodegradable straw. The biodegradable plant fiber and PBS material serve as raw materials for the straw, and the plant fiber is transformed with plant acid to improve the natural decomposition efficiency of the biodegradable straw in the environment, reduce environmental pollution, meet the demands of environmental protection, and improve the food safety of the biodegradable straw. It also improves the economic benefit of the biodegradable straw and reduces the production cost.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 21, 2023
    Inventor: Chien-Chung Huang
  • Publication number: 20230380742
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 30, 2023
    Inventors: Chun-Te HUANG, Kai-Chih PAI, Tsai-Jung WANG, Min-Shian WANG, Yan-Nan LIN, Cheng-Hsu CHEN, Chun-Ming LAI, Ruey-Kai SHEU, Lun-Chi CHEN, Chieh-Liang WU, Chien-Lun LIAO, Ta-Chun HUNG, Chien-Chung HUANG, Chia-Tien HSU, Shang-Feng TSAI
  • Publication number: 20230369224
    Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 11810857
    Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20230343911
    Abstract: A packaging structure, which includes a metal bracket, a driver chip, a light-emitting component, a packaging member and a metal cover plate. The metal bracket includes a plurality of pins, and first and second surfaces oppositely disposed. The driver chip is disposed on the first surface, and configured to control a light-emitting state of the light-emitting component. The light-emitting component is disposed on the second surface and electrically connected to the driver chip through the metal bracket. The packaging structure is disposed on the metal bracket, and configured to fix the metal bracket and enclose the driver chip and the light-emitting component. The pins are disposed surrounding the driver chip and are partially exposed from the packaging member. The metal cover plate is disposed on a side of the driver chip away from the light-emitting component, covering an entire surface of the driver chip.
    Type: Application
    Filed: October 19, 2022
    Publication date: October 26, 2023
    Applicant: BRIGHTEK OPTOELECTRONICS CO., LTD. (Jiangsu)
    Inventors: Feng WU, Chih-Hung TZENG, Chien-Chung HUANG
  • Patent number: 11800812
    Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Publication number: 20230276715
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
  • Publication number: 20230263068
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 17, 2023
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Patent number: 11683991
    Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 11665971
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Patent number: 11580643
    Abstract: A system for facilitating medical image interpretation includes a processing unit and a display control unit. The processing unit includes a location information module generating a reference location indicator, and a feature marking module generating indication markers. The display control unit is in signal connection with the processing unit and a display device. The display control unit includes an image displaying module controlling the display device to display tissue images, and an auxiliary information displaying module controlling the display device to display, for each of the tissue images displayed by the display device, the reference location indicator and the indication markers together on the tissue image.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 14, 2023
    Assignee: V5 TECHNOLOGIES CO., LTD.
    Inventors: Chien-Chung Huang, Chien-Ting Yang, Tzu-Kuei Shen, Yu-Hsun Kao, Kuo-Tung Hung, Yueh-Heng Lee
  • Patent number: 11527476
    Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai