Patents by Inventor Chien-Chung Huang
Chien-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11665971Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.Type: GrantFiled: August 23, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
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Patent number: 11580643Abstract: A system for facilitating medical image interpretation includes a processing unit and a display control unit. The processing unit includes a location information module generating a reference location indicator, and a feature marking module generating indication markers. The display control unit is in signal connection with the processing unit and a display device. The display control unit includes an image displaying module controlling the display device to display tissue images, and an auxiliary information displaying module controlling the display device to display, for each of the tissue images displayed by the display device, the reference location indicator and the indication markers together on the tissue image.Type: GrantFiled: September 30, 2020Date of Patent: February 14, 2023Assignee: V5 TECHNOLOGIES CO., LTD.Inventors: Chien-Chung Huang, Chien-Ting Yang, Tzu-Kuei Shen, Yu-Hsun Kao, Kuo-Tung Hung, Yueh-Heng Lee
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Patent number: 11527476Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: GrantFiled: January 7, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
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Publication number: 20220367794Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 11411176Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: GrantFiled: December 14, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20220190237Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
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Publication number: 20220084937Abstract: A semiconductor structure and a method of forming the same are provided. A method includes depositing a dielectric layer over a conductive feature. The dielectric layer is patterned to form an opening therein. The opening exposes a first portion of the conductive feature. A first barrier layer is deposited on a sidewall of the opening. The first portion of the conductive feature remains exposed at the end of depositing the first barrier layer.Type: ApplicationFiled: January 7, 2021Publication date: March 17, 2022Inventors: Yao-Min Liu, Chia-Pang Kuo, Chien Chung Huang, Chih-Yi Chang, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
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Patent number: 11271150Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.Type: GrantFiled: May 4, 2020Date of Patent: March 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
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Publication number: 20220068826Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Chia-Pang Kuo, Chih-Yi Chang, Ming-Hsiao Hsieh, Wei-Hsiang Chan, Ya-Lien Lee, Chien Chung Huang, Chun-Chieh Lin, Hung-Wen Su
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Publication number: 20210384418Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
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Publication number: 20210366117Abstract: A system for facilitating medical image interpretation includes a processing unit and a display control unit. The processing unit includes a location information module generating a reference location indicator, and a feature marking module generating indication markers. The display control unit is in signal connection with the processing unit and a display device. The display control unit includes an image displaying module controlling the display device to display tissue images, and an auxiliary information displaying module controlling the display device to display, for each of the tissue images displayed by the display device, the reference location indicator and the indication markers together on the tissue image.Type: ApplicationFiled: September 30, 2020Publication date: November 25, 2021Inventors: Chien-Chung HUANG, Chien-Ting YANG, Tzu-Kuei SHEN, Yu-Hsun KAO, Kuo-Tung HUNG, Yueh-Heng LEE
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Publication number: 20210347985Abstract: Disclosed is a biodegradable composition, including: 5 to 90 percent by weight of polylactic acid (PLA), 5 to 80 percent by weight of plant fiber, and 5 to 70 percent by weight of maleic anhydride-grafted polybutylene succinate (PBS-g-MA), acrylic acid-grafted polybutylene succinate (PBS-g-AA), or silane coupling agent-grafted polybutylene succinate (PBS-g-Silane). The article manufactured therefrom is not only biodegradable but also has an enhanced heat deformation temperature, impact resistance and tensile strength. Further, by so limiting the proportion of each component, compatibility between the components may be increased and crystallization of polylactic acid may be facilitated.Type: ApplicationFiled: September 7, 2018Publication date: November 11, 2021Inventor: Chien-Chung HUANG
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Patent number: 11101429Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.Type: GrantFiled: April 1, 2019Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
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Patent number: 11083243Abstract: A method for manufacturing a shoe part includes: the first mixing step, the standing step, the second mixing step, the setting step, and the hot press forming step. The invention mainly uses the waste coffee grounds material as raw material to manufacture the shoe part. In addition to the aroma of coffee, the shoes have the functions of deodorization and dehumidification while being worn by the user, thereby achieving multiple objectives of environmentally friendly materials, low cost, strong structure and environmentally friendly after-use treatment.Type: GrantFiled: January 22, 2019Date of Patent: August 10, 2021Assignee: CCILU International Inc.Inventors: Shu-Li Chang, Chien-Chung Huang, Yeng-Fong Shih
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Patent number: 11058171Abstract: The present invention provides a shoe material part mainly composed of a coffee ground material, a porous material and a rubber-plastic material, and is made of a recycled waste porous material and recycled waste coffee grounds, which can improve the value of waste recycling and reuse, and reduce environmental pollution, in addition to reducing waste, there will be no residue pollution of natural ecology and other issues in the subsequent environmental recycling, quite in line with environmental requirements. In addition, the present invention has the function of natural deodorization, because the coffee grounds can naturally diffuse the aroma of coffee, and the characteristics of better deodorization and air permeability of the coffee grounds can be used to reduce the foul smell of a user's foot.Type: GrantFiled: January 22, 2019Date of Patent: July 13, 2021Assignee: CCILU INTERNATIONAL INC.Inventors: Shu-Li Chang, Chien-Chung Huang, Yeng-Fong Shih
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Publication number: 20210098695Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20210074909Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.Type: ApplicationFiled: November 24, 2020Publication date: March 11, 2021Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
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Patent number: 10923461Abstract: A light-emitting module and a tandem light-emitting device include an insulating housing, a control chip, a light-emitting unit, and a plurality of pins. The insulating housing has an upper accommodating space and a lower accommodating space, the lower accommodating space is below the upper accommodating space directly, and the upper accommodating space forms an opening at the upper end of the insulating housing. The control chip is located in the lower accommodating space. The light-emitting unit is located in the upper accommodating space and is electrically connected to the control chip. A plurality of pins are exposed outside the insulating housing. The control chip can receive an electrical signal transmitted by an external control device through the pins to control the illumination of the light-emitting unit.Type: GrantFiled: August 15, 2019Date of Patent: February 16, 2021Assignees: BRIGHTEK OPTOELECTRONIC (SHENZHEN) CO., LTD., BRIGHTEK OPTOELECTRONIC CO., LTD.Inventors: Chien-Chung Huang, Hsin-Nu Li, Jun-Jie He
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Patent number: 10868239Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: GrantFiled: October 25, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Patent number: 10862023Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.Type: GrantFiled: January 8, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu