Patents by Inventor Chien-Chung Huang

Chien-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070258586
    Abstract: A method of processing a transport stream having a plurality of packets to output a protected transport stream includes providing a set of secret keys having a predetermined number of secret keys; generating a key indication value; selecting a secret key from the set of secret keys according to the key indication value to form a selected secret key; generating an encrypted packet based on the selected secret key and a packet in the transport stream by: encrypting the payload of the packet according to the selected secret key, and storing the key indication value in the sync field; and generating the protected transport stream based on the encrypted packet. Where each packet comprising a packet header and a payload, the packet header comprising a sync field, and the sync field carrying a preset sync pattern.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 8, 2007
    Inventors: Chien-Chung Huang, Freimann Felix, Yuan-Liang Cheng, Tung-Hao Huang
  • Publication number: 20070243686
    Abstract: A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the addition of the foregoing certain gas, it can reduce the compressive stress, thereby increasing PMOS drive current gain.
    Type: Application
    Filed: April 17, 2006
    Publication date: October 18, 2007
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang
  • Publication number: 20070225826
    Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.
    Type: Application
    Filed: March 21, 2006
    Publication date: September 27, 2007
    Inventors: Chien-Chung Huang, Yuan-Liang Cheng, Tung-Hao Huang, You-Min Yeh, Chung-Yu Chang
  • Publication number: 20070170963
    Abstract: An exemplary CPU frequency regulating circuit includes a detecting circuit, and a comparing circuit. The detecting circuit receives a PWM signal from a super I/O chipset, and converts the PWM signal to a load voltage responsive to a workload of a CPU. The comparing circuit is coupled to the detecting circuit for receiving the load voltage, and compares the load voltage with a reference voltage, and adjusts a frequency of the CPU according to a result of the comparison.
    Type: Application
    Filed: November 25, 2006
    Publication date: July 26, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIN-WANG LIANG, HAN-CHIANG CHUANG, HUNG-JU CHEN, CHIEN-CHUNG HUANG, WEN-LUNG LIANG, CHIH-LIANG KUO
  • Publication number: 20070117370
    Abstract: A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, wherein the stress material inside the gap has a seam. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.
    Type: Application
    Filed: November 24, 2005
    Publication date: May 24, 2007
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang
  • Publication number: 20070117375
    Abstract: A method of forming a contact is provided. A substrate having at least two conductive devices is provided. A spacing is located between the two conductive devices. A first dielectric layer is formed over the substrate to cover the two conductive devices and the spacing. A seam is formed in the first dielectric layer within the spacing. Then, a portion of the first dielectric layer is removed to form an opening so that the width of the seam is expanded. A second dielectric layer is formed over the first dielectric layer to fill the opening. A portion of the second dielectric layer and a portion of the first dielectric layer within the spacing are removed until a portion of the surface of the substrate is exposed and a contact opening is formed in the location for forming the contact. Finally, conductive material is deposited to fill the contact opening.
    Type: Application
    Filed: November 24, 2005
    Publication date: May 24, 2007
    Inventors: Chao-Lon Yang, Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Shao-Ta Hsu
  • Publication number: 20070105292
    Abstract: A method for fabricating high tensile stress film and strained-silicon transistors. First, a semiconductor substrate is provided and a gate, at least a spacer, and a source/drain region are formed on the semiconductor substrate. Next, n deposition processes are performed to form n layers of high tensile stress film over the surface of the gate and the source/drain region, in which each high tensile stress film is treated with a heat treatment process and n is greater than or equal to two.
    Type: Application
    Filed: November 7, 2005
    Publication date: May 10, 2007
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Hsiu-Lien Liao, Chien-Chung Huang
  • Publication number: 20070105367
    Abstract: A method for forming barrier layers comprises steps of providing a conductive layer, forming a first dielectric layer on the conductive layer, the first dielectric layer having a via therein, forming a first metal layer covering the first dielectric layer and the conductive layer, forming a layer of metallized materials on the first metal layer, removing the layer of metallized materials above the via bottom in the first dielectric layer, and leaving the layer of metallized materials remaining on a sidewall of the via in the first dielectric layer; and forming a second metal layer covering the layer of metallized materials. The accomplished barrier layers will have lower resistivity in the bottom via of the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Yu-Ru Yang, Chien-Chung Huang
  • Publication number: 20070087573
    Abstract: A pre-treatment method for physical vapor deposition of a metal layer is provided. A substrate is first provided and then a dry cleaning process is performed to the substrate using a chemical etching process, in which the chemical etching process causes a reaction to the oxide. Thereafter, an annealing process is performed, followed by a cooling process. Due to the treatment prior to depositing of the metal layer, subsequent metal layers from ill effects are prevented.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Yi-Yiing Chiang, Chao-Ching Hsieh, Tzung-Yu Hung, Yu-Lan Chang, Chien-Chung Huang, Yi-Wei Chen
  • Patent number: 7199040
    Abstract: A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: April 3, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Ru Yang, Chien-Chung Huang
  • Publication number: 20070032077
    Abstract: A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed to remove the metallic layer outside the opening. One main feature of the present invention is the performance of at least a high temperature treatment after the metallic layer is formed. Due to the high temperature treatment, internal stress between different layers is released.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Tzung-Yu Hung, Chien-Chung Huang, Chao-Ching Hsieh, Chia-Lin Hsu
  • Patent number: 7145275
    Abstract: A bearing assembly with auxiliary magnetism comprises a shaft, a fan base and a bearing. The fan base provides a hollow shaft seat with a receiving space to accommodate the shaft. The bearing fits with the shaft for supporting the shaft. A magnetic part surrounds the shaft to attract the shaft such that the fan blade hub can be fixed at a specific position.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: December 5, 2006
    Assignee: Asia Vital Component Co., Ltd.
    Inventors: Ching-Min Yang, Chien-Chung Huang
  • Patent number: 7133735
    Abstract: A system and method thereof for experiment management. A storage device stores an experiment plan record, a merge constraint and an integration rule. A processing unit configured to acquire a first experiment plan from the experiment plan record, and a second experiment plan. The processing unit generates an integrated experiment plan by merging the first experiment plan and the second experiment plan according to the merge constraint and the integration rule, and stores the integrated experiment plan to the storage device.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Wen-Chang Kuo, Chien-Chung Huang, Huei-Wen Yang, Yi-Lin Huang
  • Publication number: 20060240666
    Abstract: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the silicide to break up lattice structure of the silicide, so that the problem of junction leakage induced by spiking and piping diffusion under high temperature during a subsequent second annealing process is avoided.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Chao-Ching Hsieh, Yi-Yiing Chiang, Chien-Chung Huang, Po-Chao Tsou, Kirk Hsu, Tony Lin, Le-Tien Jung
  • Publication number: 20060211242
    Abstract: A method of forming a plug is provided. First, a substrate comprising at least a dielectric layer is provided, and a patterned hard mask is formed on the dielectric layer to define a position of at least a plug hole. Subsequently, the dielectric layer is etched for forming the plug hole. A barrier layer and a conductive layer are formed on the substrate, and the plug hole is filled by the conductive layer. Thereafter, first, second, and third chemical mechanical polishing processes are performed in turn. Finally, a fourth chemical mechanical polishing process is performed to remove portions of the conductive layer.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 21, 2006
    Inventors: Chia-Lin Hsu, Chih-Chan Yu, Chien-Chung Huang
  • Publication number: 20060199305
    Abstract: A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.
    Type: Application
    Filed: November 24, 2005
    Publication date: September 7, 2006
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
  • Publication number: 20060167578
    Abstract: A system and method thereof for experiment management. A storage device stores an experiment plan record, a merge constraint and an integration rule. A processing unit configured to acquire a first experiment plan from the experiment plan record, and a second experiment plan. The processing unit generates an integrated experiment plan by merging the first experiment plan and the second experiment plan according to the merge constraint and the integration rule, and stores the integrated experiment plan to the storage device.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Inventors: Wen-Chang Kuo, Chien-Chung Huang, Huei-Wen Yang, Yi-Lin Huang
  • Publication number: 20060157080
    Abstract: A cleaning method according to the present invention is provided. The method includes at least two stages of cleaning processes. In the first stage, dilute HF is provided as a cleaning solution, and a brushing process is performed. In the second stage, dilute HF is also provided as a cleaning solution, and a washing process is performed. A pre-cleaning process and a post-cleaning process are further provided according to the present invention. The pre-cleaning method is performed before the brushing process, and the post-cleaning method is performed after the washing process. In addition, the pre-cleaning process and the post-cleaning process are a brushing process or a washing process adopting NH4OH as a cleaning solution.
    Type: Application
    Filed: January 20, 2005
    Publication date: July 20, 2006
    Inventors: Teng-Chun Tsai, Hsin-Kun CHU, Chien-Chung Huang
  • Publication number: 20060036697
    Abstract: An email system and method thereof. The system includes at least a mail agent to receive at least one email message with a flag. The mail agent assesses the flag, and performs a predefined process including storing mail content of the email message in a database, generating a new email message comprising a link to the mail content of the email message in the database, and forwarding the new email message to recipients of the email message if the flag is a predefined value.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Jun-Liang Lin, Chien-Chung Huang, Dah-Chung Chen, Teng-Hsiang Hsu, Shih-Wei Chen, Chih-Yang Wang
  • Publication number: 20050283498
    Abstract: A method of building a problem troubleshooting database for use in a semiconductor manufacturing system includes storing semiconductor manufacturing problem data in a problem troubleshooting database; storing cause data in the problem troubleshooting database, the cause data being associated with respective problem data; storing solution data in the problem troubleshooting database, the solution data being associated with respective semiconductor manufacturing problem data and cause data; evaluating the effectiveness of the solution data; and updating the solution data with information with respect to the effectiveness determined in the evaluating step.
    Type: Application
    Filed: June 22, 2004
    Publication date: December 22, 2005
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chang Kuo, Tien-Der Chiang, Chien-Chung Huang, Mu-Tsang Lin, Yi-Lin Huang, Chun-Yi Chen, Chi Wang