Patents by Inventor Chien-Chung Hung

Chien-Chung Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100080034
    Abstract: A magnetic shift register includes at least a magnetic memory track of which several magnetic walls separate the memory track into multiple magnetic domains to serve as magnetic binary memory cells. The magnetic memory track includes multiple data regions. Each data region has multiple of the magnetic binary memory cells for storing bit data at a quiescent state and registering at least one of the bit data shifted from the adjacent data region at a shifting state. Wherein, the bit data of the magnetic binary memory cells is shifted between the adjacent two data region under an operation current.
    Type: Application
    Filed: November 17, 2008
    Publication date: April 1, 2010
    Applicant: Industrial Technology Research Institute
    Inventor: Chien-Chung Hung
  • Publication number: 20090316472
    Abstract: A magnetic random access memory (MRAM) including multiple memory cells for forming an array is provided. Each memory cell has a magnetic free stack layer and a pinned stack layer. A magnetization of the pinned stack layer is set toward a predetermined direction. The magnetic free stack layer has a magnetic easy axis. Two magnetic easy axes of adjacent two memory cells are substantially perpendicular to each other.
    Type: Application
    Filed: April 23, 2008
    Publication date: December 24, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ding-Yeong Wang, Yuan-Jen Lee, Chien-Chung Hung
  • Patent number: 7577019
    Abstract: A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at least the two magnetic memory units are stacked to form a circuit of serial connection or parallel connection. The circuit and the read bit line are connected. The switching device is connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit with a ground voltage. Furthermore, a plurality of the multi-bit magnetic cells is used to form a magnetic memory device.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: August 18, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Yuan-Jen Lee
  • Patent number: 7577017
    Abstract: A method for accessing a memory cell of a magnetoresistive random access memory (MRAM) device, where the memory cell includes a plurality of memory units, includes writing the memory cell by identifying ones of the memory units having stored therein a datum different from a datum to be written thereto; and simultaneously writing all of the ones of the memory units. An MRAM device includes a plurality of write word lines, a plurality of write bit lines, and a plurality of memory cells. Each memory cell includes a plurality of memory units. Each memory unit includes a free magnetic region having one or more easy axes non-perpendicular to the write bit lines and non-perpendicular to the write word lines, a pinned magnetic region, and a tunneling barrier between the free magnetic region and the pinned magnetic region.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: August 18, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Yuan-Jen Lee
  • Patent number: 7554836
    Abstract: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 30, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Young-Shying Chen, Chung-Chih Wang, Chia-Pao Chang, Chien-Chung Hung
  • Patent number: 7539049
    Abstract: A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: May 26, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Ding-Yeong Wang, Yuan-Jen Lee
  • Patent number: 7515458
    Abstract: A magnetic memory cell, used in a magnetic memory device, includes a stacked magnetic pinned layer, serving as a part of the base structure. The stacked magnetic pinned stacked layer has a top pinned layer and a bottom pinned layer, between which there is a sufficient large magnetic coupling force to maintain magnetization of the top pinned layer on a reference direction. A tunnel barrier layer is disposed on the stacked magnetic pinned layer. A magnetic free stacked layer is disposed on the tunnel barrier layer. The magnetic free stacked layer includes a bottom free layer having a bottom magnetization and a top free layer having a top magnetization. When no assisted magnetic field is applied, the bottom magnetization is anti-parallel to the top magnetization and is perpendicular to the reference direction on the top pinned layer. A magnetic bias layer can be also disposed on the top free layer.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: April 7, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Yung-Hsiang Chen, Ming-Jer Kao, Yuan-Jen Lee, Yung-Hung Wang
  • Publication number: 20090039450
    Abstract: A structure of magnetic memory cell including a first anti-ferromagnetic layer is provided. A first pinned layer is formed over the first anti-ferromagnetic layer. A tunneling barrier layer is formed over the first pinned layer. A free layer is formed over the tunneling barrier layer. A metal layer is formed over the free layer. A second pinned layer is formed over the metal layer. A second anti-ferromagnetic layer is formed over the second pinned layer.
    Type: Application
    Filed: December 25, 2007
    Publication date: February 12, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Jen Lee, Ding-Yeong Wang, Chien-Chung Hung
  • Publication number: 20090040663
    Abstract: A magnetic memory includes a stack, a first writing wire, and a second writing wire. The stack includes a magnetic pinned layer, a tunnel barrier insulating layer, and a magnetic free layer, so as to form a magnetic tunnel junction (MTJ). The MTJ has an easy axis. The first writing wire is disposed under the stack. The included angle between the first writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on a projected plane. The second writing wire is disposed above the stack. The included angle between the second writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on the projected plane.
    Type: Application
    Filed: October 9, 2008
    Publication date: February 12, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Yuan-Jen Lee, Ding-Yeong Wang, Chien-Chung Hung
  • Publication number: 20090034322
    Abstract: A magnetic random access memory includes at least a first-direction write current line and multiple second-direction write current line, intersecting with the first-direction write current line in substantial perpendicular and forming several intersecting regions. Multiple magnetic memory cells are respectively located at the intersecting regions for receiving an induced magnetic field in a time sequence. Every at least two adjacent memory cells are in parallel or series connection, to form at least one memory unit. An easy axis of a free layer of each magnetic memory cell is substantially perpendicular to a magnetization of a pinned layer. The easy axis and the first-direction write current line form an including angle of about 45°. A read bit-line circuit connects to a first terminal of the memory unit. A read word-line circuit connects to a second terminal of the memory unit.
    Type: Application
    Filed: November 27, 2007
    Publication date: February 5, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Ding-Yeong Wang, Yuan-Jen Lee
  • Publication number: 20090010087
    Abstract: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in.
    Type: Application
    Filed: December 28, 2007
    Publication date: January 8, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Young-Shying CHEN, Chung-Chih WANG, Chia-Pao CHANG, Chien-Chung HUNG
  • Publication number: 20090003043
    Abstract: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current.
    Type: Application
    Filed: July 18, 2008
    Publication date: January 1, 2009
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Yuan-Jen Lee, Lien-Chang Wang
  • Patent number: 7463510
    Abstract: A magnetoresistive random access memory (MRAM) device includes a memory cell corresponding to one read bit line, one read word line, one write word line, and two or more write bit lines. The memory cell includes a first memory unit and a second memory unit each corresponding to a respective write bit line. Each of the first and second memory units comprises: a free magnetic region having a first easy axis, a pinned magnetic region having a second easy axis, and a tunneling barrier between the free magnetic region and the pinned magnetic region.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: December 9, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Yuan-Jen Lee, Ming-Jer Kao
  • Publication number: 20080298119
    Abstract: A multi-bit magnetic memory cell in a stacked structure controlled by at least one read bit line and one read word line is provided. The multi-bit magnetic memory cell includes at least two magnetic memory units and a switching device. Each magnetic memory unit has a magneto-resistance value and at least the two magnetic memory units are stacked to form a circuit of serial connection or parallel connection. The circuit and the read bit line are connected. The switching device is connected to the circuit, wherein the switching device is controlled by the read word line to be conducting or non-conducting so as to connect the circuit with a ground voltage. Furthermore, a plurality of the multi-bit magnetic cells is used to form a magnetic memory device.
    Type: Application
    Filed: September 12, 2007
    Publication date: December 4, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Yuan-Jen Lee
  • Publication number: 20080247096
    Abstract: A magnetic memory including a stack, a first writing wire, and a second writing wire is provided. The stack includes a magnetic pinned layer, a tunnel barrier insulating layer, and a magnetic free layer, so as to form a magnetic tunnel junction (MTJ). The MTJ has an easy axis. The first writing wire is disposed under the stack. The included angle between the first writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on a projected plane. The second writing wire is disposed above the stack. The included angle between the second writing wire and the easy axis of the MTJ is smaller than 45 degrees and greater than 0 degrees on the projected plane.
    Type: Application
    Filed: May 29, 2007
    Publication date: October 9, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Jen Lee, Ding-Yeong Wang, Chien-Chung Hung
  • Publication number: 20080239800
    Abstract: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 2, 2008
    Inventors: Chi-Ming Chen, Chien-Chung Hung, Young-Shying Chen, Lien-Chang Wang
  • Patent number: 7420837
    Abstract: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: September 2, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Ming-Jer Kao, Yuan-Jen Lee, Lien-Chang Wang
  • Publication number: 20080180988
    Abstract: A direct writing method of a magnetic memory cell is provided. The magnetic memory cell includes a magnetic free stacked layer having a bottom and a top ferromagnetic layer. The bottom and top ferromagnetic layers respectively have a bi-directional easy axis in substantially the same direction. The method includes applying a first magnetic field in the direction of the bi-directional easy axis and performing a writing operation. To write a first memory state, a second magnetic field is supplied at a first side of the bi-directional easy axis with a first including angle. To write a second memory state, a third magnetic filed is supplied at a second side of the bi-directional easy axis with a second including angle. At least one of the bottom and top ferromagnetic layers has a unidirectional easy axis in different direction from the bi-directional easy axis.
    Type: Application
    Filed: May 27, 2007
    Publication date: July 31, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yuan-Jen Lee, Chien-Chung Hung
  • Patent number: 7397694
    Abstract: A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 8, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Ming Chen, Chien-Chung Hung, Young-Shying Chen, Lien-Chang Wang
  • Patent number: 7372724
    Abstract: A method for accessing data on a magnetic memory is provided, wherein the data is accessed in a toggle mode. A first current line and a second current line are used for providing operation currents. The data accessing method includes a data changing operation for changing a data stored in a magnetic memory cell. During a first stage, a current in a first direction is supplied to the first current line, and a current in the first direction is simultaneously supplied to the second current line. During a stage before stopping supplying magnetic field, a current in the first direction is supplied to the first current line, and a current in the first direction is simultaneously supplied to the second current line to offset at least a portion of the biased magnetic field.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 13, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Yuan-Jen Lee, Chien-Chung Hung