Abstract: An electronic device is provided. The electronic device includes: a first substrate, a first light-emitting unit, a wall structure, and a first optical film. The first light-emitting unit is disposed on the first substrate. The wall structure is disposed on the first substrate, and includes a first opening corresponding to the first light-emitting unit. At least a portion of the first optical film is disposed on the first light-emitting unit, and the at least a portion of the first optical film is disposed in the first opening.

Abstract: An electronic device includes: a substrate; a plurality of electronic components disposed on the substrate, wherein there is a first pitch between two adjacent electronic components in a first direction; and a protective glue disposed on the substrate and the electronic components, and provided with at least one groove disposed between the two adjacent electronic components, wherein a distance between an edge of one of the two adjacent electronic components and the at least one groove satisfies an equation: 0.3 mm ? D ? 1 < ( P / 2 ) , where D1 is the distance between the edge of the one of the two adjacent electronic components and the at least one groove, and P is the first pitch.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Provided are a manufacturing method of an overlay mark and an overlay measurement method. The manufacturing method includes the following steps. A first stitching overlay mark structure having a plurality of first patterns is formed on a first layer. A second layer is formed on the first layer. A second stitching overlay mark structure having a plurality of second patterns is formed on the second layer. The second stitching overlay mark structure is located above the first stitching overlay mark structure, and from the top view on the second layer, the second patterns and the first patterns are alternately arranged.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: Examples of a supporting assembly for supporting an installable component are described. The supporting assembly comprises a supporting member. The supporting assembly may further include a latch bar extending longitudinally to support the installable component. The supporting assembly may further include a coupling arm and a control knob. In an example, the control knob may be rotatable, and is to control rotation of the latch bar.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A holding device for retaining an installable component in a chassis of a computing device may includes a longitudinally extending first arm, and a movably coupled second arm. The holding device may further include a first engaging portion at first end of the holding device, and a second engaging portion at the second end of the holding device. The engaging portions may couple the holding device to the chassis of the computing device. Furthermore, the holding device may comprise a gripping member. The gripping member is to securely retain the installable component within the chassis of the computing device, and is movable across the length of the holding device.

Abstract: A photomask set including a first photomask and a second photomask is provided. The first photomask includes a first pattern. The first pattern includes a first main portion and a first stitching portion connected to each other. The first stitching portion includes a first matching portion and a first overlapping portion connected to each other. The second photomask includes a second pattern. The second pattern includes a second main portion and a second stitching portion connected to each other. The second stitching portion includes a second matching portion and a second overlapping portion connected to each other. After the first photomask is aligned with the second photomask, the first matching portion matches the second matching portion, the first overlapping portion overlaps the second pattern, and the second overlapping portion overlaps the first pattern.

Abstract: The present invention provides a magnetic computer case comprising a first plate body, a second plate body and a third plate body. The first plate body is provided with a first connection part, where the first connection part is provided at a corner of the first plate body. The second plate body is provided on one side of the first plate body and provided with a second connection part, where the second connection part is provided at a corner of the second plate body. The second plate body is provided with a third connection part and the third connection part is provided at a corner of the third plate body, such that the first plate body is movably and magnetically connected with the third plate body and the second plate body.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The second layer includes metal and oxygen. The first layer is first layer over the gate dielectric layer and may include one of titanium nitride (TiN), titanium silicon nitride (TiSiN), or tantalum carbide (TaC). Minimization of equivalent oxide thickness may result.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A method used for object tracking includes: using a specific object model to generate a first vector of a first ratio object and a second vector of a second ratio object of an image in an object detection bounding box of a specific frame; generating an identity label of an object within the bounding box according to the first vector, the second vector, and M first ratio reference vectors and M second ratio reference vectors stored in an object vector database.

Abstract: A method of performing person re-identification includes: obtaining a person feature vector according to an extracted image containing a person; obtaining state information of the person according to a state of the person in the extracted image; comparing the person feature vector with a plurality of registered person feature vectors in a database; when the person feature vector successfully matches a first registered person feature vector of the plurality of registered person feature vectors, identifying the person as a first identity corresponding to the first registered person feature vector; and selectively utilizing the person feature vector to update one of the first registered person feature vector and at least one second registered person feature vector that correspond to the first identity according to the state information.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.