Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: EUV masks and methods of fabrication thereof are described herein. An exemplary method includes receiving an EUV mask having a multilayer structure, a capping layer disposed over the multilayer structure, a patterned absorber layer disposed over the capping layer, and a patterned hard mask disposed over the patterned absorber layer. The method further includes removing the patterned hard mask by performing a first etching process to partially remove the patterned hard mask and performing a second etching process to remove a remainder of the patterned hard mask. The first etching process uses a first etchant, and the second etching process uses a second etchant. The second etchant is different than the first etchant. In some embodiments, the first etchant is a halogen-based plasma (e.g., a Cl2 plasma), and the second etchant is a halogen-and-oxygen-based plasma (e.g., a Cl2+O2 plasma).

Abstract: A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.

Abstract: A method for beam management performed by a UE is provided. The method includes: receiving a DCI format in a first BWP based on a first QCL assumption specific to the first BWP, the DCI format scheduling a PDSCH reception in a second BWP; receiving an RRC configuration that includes a plurality of candidate TCI states associated with a serving cell in which the PDSCH is scheduled; receiving a MAC CE that indicates a subset of the plurality of candidate TCI states for activation in the second BWP; determining a second QCL assumption specific to the second BWP based on one TCI state in the subset; and receiving the PDSCH in the second BWP based on the second QCL assumption.

Abstract: A liquid-cooling heat dissipation device which comprises a cooling plate, a heat dissipator having a working liquid therein, and at least two conduits connecting the cold plate to the heat dissipator is described. A surface of the cooling plate is configured to contact a heat-generating component, thereby transferring the heat generated by the heat-generating component to the cooling plate and conducting the heat away to the heat dissipator via a working liquid.

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Abstract: An electronic device is provided, including a substrate, and a plurality of first bonding pads. The substrate includes a bonding area. The plurality of first bonding pads are disposed on the substrate and disposed in the bonding area. A part of the plurality of first bonding pads are arranged along a first direction, and another part of the plurality of first bonding pads are arranged along a second direction. There is an included angle between the first direction and the second direction, and the included angle is greater than 0 degrees and less than 90 degrees.

Abstract: A laser slicing apparatus, in which a laser module provides a laser beam, and a light splitting element of a focusing lens set splits the laser beam into a plurality of focused laser beams to form a plurality of induce lines having first laser modified cracks in a modified layer at a predetermined depth inside a substrate. A rotating module rotates the light splitting element with an angle, and the light splitting element converts the focused laser beams according to this angle to form a plurality of modified groups between the induce lines. Each modified group includes a plurality of modified lines having second laser modified cracks, and the first laser modified cracks and the second laser modified cracks are connected to each other to form a continuous laser modified crack in the modified layer at the predetermined depth inside the substrate, thereby speeding up the laser slicing production.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: An electronic device is provided. The electronic device includes: a first substrate, a first light-emitting unit, a wall structure, and a first optical film. The first light-emitting unit is disposed on the first substrate. The wall structure is disposed on the first substrate, and includes a first opening corresponding to the first light-emitting unit. At least a portion of the first optical film is disposed on the first light-emitting unit, and the at least a portion of the first optical film is disposed in the first opening.

Abstract: An electronic device includes: a substrate; a plurality of electronic components disposed on the substrate, wherein there is a first pitch between two adjacent electronic components in a first direction; and a protective glue disposed on the substrate and the electronic components, and provided with at least one groove disposed between the two adjacent electronic components, wherein a distance between an edge of one of the two adjacent electronic components and the at least one groove satisfies an equation: 0.3 mm ? D ? 1 < ( P / 2 ) , where D1 is the distance between the edge of the one of the two adjacent electronic components and the at least one groove, and P is the first pitch.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Provided are a manufacturing method of an overlay mark and an overlay measurement method. The manufacturing method includes the following steps. A first stitching overlay mark structure having a plurality of first patterns is formed on a first layer. A second layer is formed on the first layer. A second stitching overlay mark structure having a plurality of second patterns is formed on the second layer. The second stitching overlay mark structure is located above the first stitching overlay mark structure, and from the top view on the second layer, the second patterns and the first patterns are alternately arranged.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: Examples of a supporting assembly for supporting an installable component are described. The supporting assembly comprises a supporting member. The supporting assembly may further include a latch bar extending longitudinally to support the installable component. The supporting assembly may further include a coupling arm and a control knob. In an example, the control knob may be rotatable, and is to control rotation of the latch bar.