Patents by Inventor Chien-Hao Chen

Chien-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190318932
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 17, 2019
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Publication number: 20190319113
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes forming a dielectric cap layer on the conformal film. The method includes performing an anneal process on the conformal film.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei YU, Chien-Hao CHEN
  • Publication number: 20190309744
    Abstract: A miniature cooling system includes a base metal sheet, a flow channel layer, a piezoelectrically actuated metal sheet, a piezoelectric boundary compression layer and two piezoelectric ceramic vibrators. The flow channel layer is located on the base metal sheet and includes a first chamber, a second chamber, an inlet channel, a linking channel and an outlet channel. The inlet channel links the outside environment to the first chamber. The linking channel links the first chamber and the second chamber. The outlet channel links the second chamber to the outside environment. The piezoelectrically actuated metal sheet is located on the flow channel layer. The piezoelectric boundary compression layer is located on the piezoelectrically actuated metal sheet. The piezoelectric boundary compression layer includes two containing areas, and the two containing areas are respectively located above the first chamber and the second chamber.
    Type: Application
    Filed: August 30, 2018
    Publication date: October 10, 2019
    Inventors: Yung TING, Sheuan-Perng LIN, Chien-Ping WANG, Chien-Hsiang WU, Jun-Hao CHEN
  • Patent number: 10439023
    Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 8, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
  • Publication number: 20190299205
    Abstract: A detection device adapted for detecting an analyte in a sample includes a substrate having a top surface, a sample pad, a binding pad, a cellulose pad, a nitrocellulose membrane and an absorbent pad. The sample pad is for receiving the sample. The binding pad includes a main body and a first detecting reagent disposed on the main body and is adapted for specifically binding to the analyte. The cellulose pad has a first connecting end portion and a second connecting end portion. The nitrocellulose membrane includes a membrane body and a detection zone that includes a second detecting reagent adapted for specifically binding to the analyte. The absorbent pad connects to the membrane body.
    Type: Application
    Filed: August 10, 2018
    Publication date: October 3, 2019
    Applicant: Chang Gung Memorial Hospital, Linkou
    Inventors: Tsung-Ting Tsai, Tse-Hao Huang, Chien-Fu Chen
  • Publication number: 20190302873
    Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.
    Type: Application
    Filed: March 21, 2019
    Publication date: October 3, 2019
    Inventors: Chien-Hao CHEN, Chih-Hao WU, Chih-Chuan HUANG, Sung-Bo CHEN
  • Publication number: 20190281642
    Abstract: A remote controller comprises a wireless communication interface and a processing unit. The wireless communication interface is communicatively connected with another remote controller. The processing unit is electrically connected with the wireless communication interface. The processing unit generates a first identification code and a second identification code and transmits the first identification code and the second identification code to the another remote controller through the wireless communication interface. The another remote controller transmits the first identification code and the second identification code to a controlled device to establish an indirect pairing relationship between the remote controller and the controlled device and a direct pairing relationship between the another remote controller and the controlled device. A pairing method of remote controllers is also disclosed.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 12, 2019
    Inventors: Huan-Ping SU, Chien-Hsin Su, Shih-Tsun Lai, Chien-Shuo Li, Wei-Hao Chen, Jia-Woei Jean, Chih-Yuan Su
  • Patent number: 10401728
    Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Chien-Wei Wang, Chin-Hsiang Lin
  • Patent number: 10396063
    Abstract: In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen, Jeo-Yen Lee, Jyun-Hao Chang, Shao-Huan Wang, Chien-Ying Chen
  • Patent number: 10394126
    Abstract: One of the broader forms of the present disclosure relates to a method of making a semiconductor device. The method includes exposing a photoresist layer to a radiation source and applying a hardening agent to the photoresist layer. Therefore after applying the hardening agent a first portion of the photoresist layer has a higher glass transition temperature, higher mechanical strength, than a second portion of the photoresist layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Cheng, Ching-Yu Chang, Chien-Wei Wang, Yen-Hao Chen
  • Publication number: 20190252381
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Publication number: 20190235389
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Application
    Filed: December 11, 2018
    Publication date: August 1, 2019
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Patent number: 10347741
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ju Liang, De-Wei Yu, Yi-Cheng Li, Chien-Hao Chen
  • Patent number: 10332746
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Patent number: 10312158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Cheng Li, Chien-Hao Chen, Yung-Cheng Lu, Jr-Jung Lin, Chun-Hung Lee, Chao-Cheng Chen
  • Publication number: 20190156587
    Abstract: A digital dental mesh segmentation method and a digital dental mesh segmentation device are provided. The digital dental mesh segmentation method includes: receiving a digital dental mesh, including a plurality of teeth; inserting a tooth interface separator at a tooth interface of the digital dental mesh, the tooth interface separator being at a first location; receiving a three-dimensional movement signal and a three-dimensional rotation signal to move and rotate the tooth interface separator from the first location to a second location; and segmenting the digital dental mesh according to the tooth interface separator at the second location to obtain an independent digital teeth model.
    Type: Application
    Filed: November 23, 2018
    Publication date: May 23, 2019
    Applicant: Candor Ltd.
    Inventors: Chien-Chih Huang, Cheng-Han Wu, Wen-Pin Hsu, Ting-Hui Kao, Chih-Hao Hsu, Hsuan-Hung Liu, Jen-How Wang, Chi-Kang Chen
  • Publication number: 20190131419
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: May 2, 2019
    Inventors: Yong-Tian HOU, Yuan-Shun CHAO, Chien-Hao CHEN, Cheng-Lung HUNG
  • Publication number: 20190131421
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Huang-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Patent number: 10276395
    Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee
  • Patent number: 10269799
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang