Abstract: The present invention provides a processing circuit applied to a face recognition system, which includes a characteristic value calculation module, a determination circuit and a threshold value calculation module.

Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A method of performing person re-identification includes: obtaining a person feature vector according to an extracted image containing a person; obtaining state information of the person according to a state of the person in the extracted image; comparing the person feature vector with a plurality of registered person feature vectors in a database; when the person feature vector successfully matches a first registered person feature vector of the plurality of registered person feature vectors, identifying the person as a first identity corresponding to the first registered person feature vector; and selectively utilizing the person feature vector to update one of the first registered person feature vector and at least one second registered person feature vector that correspond to the first identity according to the state information.

Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Abstract: A method used for object tracking includes: using a specific object model to generate a first vector of a first ratio object and a second vector of a second ratio object of an image in an object detection bounding box of a specific frame; generating an identity label of an object within the bounding box according to the first vector, the second vector, and M first ratio reference vectors and M second ratio reference vectors stored in an object vector database.

Abstract: An alignment system includes a light source for emitting a light. An alignment mark is disposed on a substrate for receiving the light. The alignment mark includes a first pattern and a second pattern disposed on the substrate. The first pattern includes a first region and a second region. The second pattern includes a third region and a fourth region. The first region and the third region are symmetrical with respective to a symmetrical axis. The second region and the fourth region are symmetrical with respective to the symmetrical axis. The first region includes first mark lines parallel to each other. The second region includes second mark lines parallel to each other. A first pitch is disposed between the first mark lines adjacent to each other. A second pitch is disposed between the second mark lines adjacent to each other. The first pitch is different from the second pitch.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A character recognition method includes the following operations: determining that the image of character to be identified corresponds to a matching character of several registered characters according to several vector distances to be identified between a vector of an image of character to be identified and several vectors of several registered character images of several registered characters, and storing a matching vector distance between the vector of the image of character to be identified and a vector of the matching character by a processor; and storing a data of the matching character according to the image of character to be identified when the matching vector distance is less than a vector distance threshold by the processor.

Abstract: A semiconductor structure includes a first metal gate structure and a second metal gate structure. The first metal gate structure includes a first high-k gate dielectric layer, a first work function metal layer over the first high-k gate dielectric layer, and a first intervening layer between the first high-k gate dielectric layer and the first work function metal layer. The second metal gate structure includes a second high-k gate dielectric layer and a second work function metal layer over the second high-k gate dielectric layer. The first work function metal layer and the second work function metal layer include a same material. A thickness of the first work function metal layer is less than a thickness of the second work function metal layer.

Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

Abstract: A method for training a deep learning network for face recognition includes: utilizing a face landmark detector to perform face alignment processing on at least one captured image, thereby outputting at least one aligned image; inputting the at least one aligned image to a teacher model to obtain a first output vector; inputting the at least one captured image a student model corresponding to the teacher module to obtain a second output vector; and adjusting parameter settings of the student model according to the first output vector and the second output vector.

Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, a work function metal layer over the gate dielectric layer, and a plurality of barrier granules between the gate dielectric layer and the work function metal layer. At least two adjacent barrier granules of the plurality of barrier granules are separated from each other by a portion of the work function metal layer.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: Examples of a holding device for retaining an installable component in a chassis of a computing device are described. In one example, the holding device may comprise a longitudinally extending first arm, and a movably coupled second arm. The holding device may further comprise a first engaging portion at first end of the holding device, and a second engaging portion at the second end of the holding device. The engaging portions may couple the holding device to the chassis of the computing device. Furthermore, the holding device may comprise a gripping member. The gripping member is to securely retain the installable component within the chassis of the computing device, and is movable across the length of the holding device.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.