Patents by Inventor Chien-Hao Chen

Chien-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending
    Patent number: 11289343
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220028836
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shang-Ruei WU, Chien-Yuan TSENG, Meng-Jen WANG, Chen-Tsung CHANG, Chih-Fang WANG, Cheng-Han LI, Chien-Hao CHEN, An-Chi TSAO, Per-Ju CHAO
  • Method of Tuning Threshold Voltages of Transistors
    Publication number: 20210407995
    Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: December 30, 2021
    Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
  • Defect filling in patterned layer
    Patent number: 11205709
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20210391219
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Method for forming a FinFET structure that prevents or reduces deformation of adjacent fins
    Patent number: 11183426
    Abstract: Methods of forming a material layer are provided. The material layer, such as amorphous silicon, may be formed by repeatedly depositing and annealing amorphous silicon. Periodically, an etching process may be performed to widen openings between fins or other topography if necessary. The depositing, annealing, and etching process may be repeated. Subsequently, an additional layer of amorphous silicon may be deposited to a desired thickness.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Teng, De-Wei Yu, Chien-Hao Chen
  • Semiconductor Device and Method
    Publication number: 20210358811
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20210327761
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11139274
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Motor drive system and control method therefor
    Patent number: 11133770
    Abstract: A motor drive system and a control method are provided. The motor drive system is electrically connected to a motor. The motor drive system includes two safe torque off (STO) modules to achieve a two-channel STO redundancy infrastructure, so as to improve the safety of the motor drive system. In addition, the motor drive system includes a diagnosis module to diagnose malfunction of the STO modules. It ensures the STO modules to meet the related safety requirements.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 28, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Jan Chang, Yi-Kai Chou, Po-Sung Chiang, Chien-Hao Chen
  • Cap layer and anneal for gapfill improvement
    Patent number: 11114545
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes forming a dielectric cap layer on the conformal film. The method includes performing an anneal process on the conformal film.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen
  • Semiconductor Devices and Methods of Manufacture
    Publication number: 20210273070
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 2, 2021
    Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
  • Selective silicon growth for gapfill improvement
    Patent number: 11107903
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-Chen Yang
  • INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATING THEREOF
    Publication number: 20210265479
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Yong-Tian HOU, Yuan-Shun CHAO, Chien-Hao CHEN, Cheng-Lung HUNG
  • Selective Hybrid Capping Layer for Metal Gates of Transistors
    Publication number: 20210242081
    Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.
    Type: Application
    Filed: May 27, 2020
    Publication date: August 5, 2021
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Semiconductor device and method
    Patent number: 11081396
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Transistor metal gate and method of manufacture
    Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • OBJECT DETECTION METHOD FOR STATIC SCENE AND ASSOCIATED ELECTRONIC DEVICE
    Publication number: 20210182588
    Abstract: An object detection method and an associated electronic device are provided, wherein the object detection method includes: utilizing an image processing circuit to determine whether motion occurs in an image to generate a determination result; selectively utilizing a specific bounding box to identify a target object to generate an identification result according to the determination result, wherein the specific bounding box represents a location of the target object in a previous image; and selectively updating information of the specific bounding box according to the identification result.
    Type: Application
    Filed: May 3, 2020
    Publication date: June 17, 2021
    Inventors: Chao-Hsun Yang, Shang-Lun Chan, Shih-Tse Chen, Chien-Hao Chen
  • ELECTRICAL CONNECTORS WITH LINK MEMBERS
    Publication number: 20210176884
    Abstract: An example electrical connector includes a body to receive a circuit board. The body includes a first end and a second end. The electrical connector also includes a first latch rotatably attaches to the first end. The electrical connector further includes a second latch rotatably attaches to the second end. The electrical connector further includes a link member attached to the body. In response to a rotation of the first latch, the link member is to slide across the body from the first latch towards the second latch to rotate the second latch.
    Type: Application
    Filed: March 14, 2017
    Publication date: June 10, 2021
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Cary HUNG, Chien Hao CHEN
  • Integrated circuit metal gate structure
    Patent number: 11004950
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung