Patents by Inventor Chien-Hao Chen

Chien-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor and semiconductor structure
    Patent number: 9076784
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 7, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • Method and System of Conducting Online Group Purchase
    Publication number: 20150149316
    Abstract: A method and system of conducting online group purchase is implemented through a computer network including a seller's computer device and a purchaser's terminal device. The method includes showing a product on a website and displaying an initial price and a time period of an online sale of the product, starting a time counter, tracking and displaying a cumulative total quantity of the product currently ordered by all purchasers since the beginning of the online sale, and updating in real time the cumulative total quantity each time a new order is received from a new purchaser. When the cumulative quantity reaches a volume threshold value, a discounted price is released for the product, which is displayed on the website. Once the time period of the online sale has elapsed, all the purchasers are notified to proceed to payment based on the discounted price.
    Type: Application
    Filed: March 7, 2014
    Publication date: May 28, 2015
    Applicant: Taobaby Ltd.
    Inventor: Chien Hao CHEN
  • Semiconductor device having a metal gate and fabricating method thereof
    Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Advanced Forming Method and Structure of Local Mechanical Strained Transistor
    Publication number: 20150108554
    Abstract: Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
    Type: Application
    Filed: December 31, 2014
    Publication date: April 23, 2015
    Inventors: Chien-Hao Chen, Tze-Liang Lee
  • Measurement method of overlay mark
    Patent number: 9007571
    Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
  • Multi-gate field-effect transistor process
    Patent number: 8999793
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Method of patterning a metal gate of semiconductor device
    Patent number: 8993452
    Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Ryan Chia-Jen Chen, Yi-Hsing Chen, Chien-Hao Chen, Donald Y. Chao, Kuo-Bin Huang
  • MOS transistor and process thereof
    Patent number: 8975666
    Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: March 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ya-Hsueh Hsieh, Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Chi-Yuan Sun, Wei-Yu Chen, Chin-Fu Lin
  • METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150061042
    Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsun-Min Cheng, Nien-Ting Ho, Chien-Hao Chen, Ching-Yun Chang, Hsin-Fu Huang, Min-Chuan Tsai, Chi-Yuan Sun, Chi-Mao Hsu
  • Integrated High-K/Metal Gate In CMOS Process Flow
    Publication number: 20150061031
    Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 5, 2015
    Inventors: Ray Chia-Jen Chen, Yi-Shien Mor, Yi-Hsing Chen, Kuo-Tai Huang, Chien-Hao Chen, Yih-Ann Lin, Jr Jung Lin
  • MEASUREMENT METHOD OF OVERLAY MARK
    Publication number: 20150055125
    Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
  • Advanced forming method and structure of local mechanical strained transistor
    Patent number: 8933503
    Abstract: Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Tze-Liang Lee
  • METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME
    Publication number: 20140374909
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.
    Type: Application
    Filed: September 9, 2014
    Publication date: December 25, 2014
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, JING-GANG LI, Min-Hsien Chen, JIAN-HONG SU
  • TRANSISTOR AND SEMICONDUCTOR STRUCTURE
    Publication number: 20140346616
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • STRUCTURE OF METAL GATE STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20140306273
    Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
  • Semiconductor structure having aluminum layer with high reflectivity
    Patent number: 8860135
    Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 14, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Wei-Yu Chen, Chin-Fu Lin, Jing-Gang Li, Min-Hsien Chen, Jian-Hong Su
  • MULTI-GATE FIELD-EFFECT TRANSISTOR PROCESS
    Publication number: 20140295634
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Application
    Filed: June 17, 2014
    Publication date: October 2, 2014
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Integrated high-k/metal gate in CMOS process flow
    Patent number: 8841731
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
  • Semiconductor structure and process thereof
    Patent number: 8836049
    Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140239419
    Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Min-Chuan Tsai, Wei-Yu Chen, Nien-Ting Ho, Tsun-Min Cheng, Chi-Mao Hsu