Patents by Inventor Chien-Hao Chen

Chien-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor metal gate and method of manufacture
    Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • OBJECT DETECTION METHOD FOR STATIC SCENE AND ASSOCIATED ELECTRONIC DEVICE
    Publication number: 20210182588
    Abstract: An object detection method and an associated electronic device are provided, wherein the object detection method includes: utilizing an image processing circuit to determine whether motion occurs in an image to generate a determination result; selectively utilizing a specific bounding box to identify a target object to generate an identification result according to the determination result, wherein the specific bounding box represents a location of the target object in a previous image; and selectively updating information of the specific bounding box according to the identification result.
    Type: Application
    Filed: May 3, 2020
    Publication date: June 17, 2021
    Inventors: Chao-Hsun Yang, Shang-Lun Chan, Shih-Tse Chen, Chien-Hao Chen
  • ELECTRICAL CONNECTORS WITH LINK MEMBERS
    Publication number: 20210176884
    Abstract: An example electrical connector includes a body to receive a circuit board. The body includes a first end and a second end. The electrical connector also includes a first latch rotatably attaches to the first end. The electrical connector further includes a second latch rotatably attaches to the second end. The electrical connector further includes a link member attached to the body. In response to a rotation of the first latch, the link member is to slide across the body from the first latch towards the second latch to rotate the second latch.
    Type: Application
    Filed: March 14, 2017
    Publication date: June 10, 2021
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Cary HUNG, Chien Hao CHEN
  • Integrated circuit metal gate structure
    Patent number: 11004950
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
  • Semiconductor Device and Method
    Publication number: 20210082768
    Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Shao-Jyun Wu, Hung-Chi Wu, Chia-Ching Lee, Pin-Hsuan Yeh, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Sheng-Liang Pan, Huan-Just Lin
  • Gate Resistance Reduction Through Low-Resistivity Conductive Layer
    Publication number: 20210083118
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20210057280
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • MOTOR DRIVE SYSTEM AND CONTROL METHOD THEREFOR
    Publication number: 20200403552
    Abstract: A motor drive system and a control method are provided. The motor drive system is electrically connected to a motor. The motor drive system includes two safe torque off (STO) modules to achieve a two-channel STO redundancy infrastructure, so as to improve the safety of the motor drive system. In addition, the motor drive system includes a diagnosis module to diagnose malfunction of the STO modules. It ensures the STO modules to meet the related safety requirements.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 24, 2020
    Inventors: Yi-Jan Chang, Yi-Kai Chou, Po-Sung Chiang, Chien-Hao Chen
  • Gap-filling germanium through selective bottom-up growth
    Patent number: 10868140
    Abstract: A method includes depositing a silicon layer on a plurality of strips. The silicon layer is etched back to remove top portions of the silicon layer, and to expose some portions of the plurality of strips. Some bottom portions of the silicon layer at bottoms of trenches between the plurality of strips remain after the etching back. A germanium layer is selectively grown from remaining portions of the silicon layer, and exposed portions of the plurality of strips remain exposed after the germanium layer is selectively grown.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Ziwei Fang, Yee-Chia Yeo
  • Selective Silicon Growth for Gapfill Improvement
    Publication number: 20200373412
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-Chen Yang
  • Power saving control apparatus and power saving control method applied to display driving circuit
    Patent number: 10817044
    Abstract: A power saving control apparatus applied to a display driving circuit is disclosed. The power saving control apparatus includes a data analysis unit, a bias control unit and a charge sharing unit. The bias control unit is used to perform bias control. The charge sharing unit is used for charge sharing. The data analysis unit is coupled to the bias control unit and the charge sharing unit respectively. The data analysis unit instantly analyzes the display data to generate an instant analysis result and dynamically adjust the setting of bias and slew rate of the bias control unit according to the instant analysis result. The data analysis unit can dynamically adjust the setting of charge sharing range and charge sharing group number needed to be performed by the charge sharing unit according to the instant analysis result.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 27, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Chien-Hao Chen, Chih-Hao Wu, Chih-Chuan Huang, Sung-Bo Chen
  • Selective silicon growth for gapfill improvement
    Patent number: 10741674
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-Chen Yang
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200251449
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Post UV cure for gapfill improvement
    Patent number: 10727064
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chih-Tang Peng, Jei Ming Chen, Shu-Yi Wang
  • Method of forming layout of semiconductor device
    Patent number: 10707213
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Manufacturing method for semiconductor pattern
    Patent number: 10707092
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • ILLUMINATION FAN CONNECTABLE WITH AT LEAST ONE ILLUMINATION FAN FOR A COMPUTER
    Publication number: 20200208832
    Abstract: An illumination fan connectable with at least one illumination fan for a computer includes a body, provided with a fan in center of the body, an illumination area on at least two sides of the fan at top of the body, a power socket and a first connector on one side of the body, and a second connector on another side of the body. The power socket is electrically connected with the first connector, the second connector, the fan and the illumination area. When the power socket is supplied with power, the fan and the illumination area of the body is respectively driven into rotation and illumination, and when the first connector of the body is connected with a second connector of a body of another illumination fan, a fan and an illumination area of the body of another illumination fan is respectively driven into rotation and illumination.
    Type: Application
    Filed: May 6, 2019
    Publication date: July 2, 2020
    Inventor: Chien-Hao CHEN
  • MANUFACTURING METHOD FOR SEMICONDUCTOR PATTERN
    Publication number: 20200203176
    Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 25, 2020
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
  • Illumination fan connectable with at least one illumination fan for a computer
    Patent number: 10690336
    Abstract: An illumination fan connectable with at least one illumination fan for a computer includes a body, provided with a fan in center of the body, an illumination area on at least two sides of the fan at top of the body, a power socket and a first connector on one side of the body, and a second connector on another side of the body. The power socket is electrically connected with the first connector, the second connector, the fan and the illumination area. When the power socket is supplied with power, the fan and the illumination area of the body is respectively driven into rotation and illumination, and when the first connector of the body is connected with a second connector of a body of another illumination fan, a fan and an illumination area of the body of another illumination fan is respectively driven into rotation and illumination.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 23, 2020
    Inventor: Chien-Hao Chen
  • Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
    Patent number: 10692785
    Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 23, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee