Abstract: A semiconductor device including a substrate, a magnetic core and a conductor coil is provided. The magnetic core is disposed on the substrate, and formed by sub-layers of different materials stacked alternatively on one another. The conductor coil is disposed on the substrate, wherein the magnetic core partially extends to a level between an upper surface of the conductor coil and a bottom surface of the conductor coil.

Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and including a conductive interconnect; and a cap layer disposed on the interconnect structure. The cap layer includes a cap portion disposed on the conductive interconnect. The cap portion includes a plurality of two-dimensional material sheets stacked on each other and has a lower surface proximate to the conductive interconnect. The lower surface of the cap portion is formed with a plurality of dangling bonds such that the cap portion is adhered to the conductive interconnect through the dangling bonds.

Abstract: A system includes a control module and a microfluidics chip. The control module includes electromagnets. The microfluidics chip includes two bead sets, a substrate, a channel layer disposed on the substrate, and a flow-control layer disposed on the channel layer. The channel layer has a central recess, channels in communication with the central recess, and cavities in communication with the channels. The flow-control layer has through holes aligned with the cavities of the channel layer. The through holes and the cavities cooperatively form wells. The flow-control layer includes micro-valves corresponding in position to the channels, and magnetic components connected to the micro-valves. A sample is disposed in one of the wells, and the bead sets are coated with aptamers and attach to another two of the wells. The electromagnets control the micro-valves to allow flow of the sample and to allow the sample to be mixed with the bead sets.

Abstract: An electronic device is disclosed. The electronic device includes an inertial measurement element and a processor. The inertial measurement element is configured to obtain a first inertial measurement data when the electronic device moves. The processor is configured to perform the following operations: establishing a mixed reality environment coordinate system in correspondence according to the real space, and calculating a starting coordinate point of the electronic device in the mixed reality environment coordinate system; converting the first inertial measurement data into a first movement vector in the mixed reality environment coordinate system according to an inertial measurement data mapping model; calculating a first spatial operation point in the mixed reality environment coordinate system according to the starting coordinate point and the first movement vector in the mixed reality environment coordinate system; and executing a 3D scene editing program with the first spatial operation point.

Abstract: An extended reality space generating apparatus and method are provided. The extended reality space generating apparatus generates a plurality of plane plates, a plate coordinate and a normal vector corresponding to each of the plane plates based on a plurality of point clouds, wherein the point clouds correspond to a real space. The extended reality space generating apparatus compares the plate coordinates and the normal vectors of the plane plates in a visual window to generate an effective plane plate set. The extended reality space generating apparatus generates an extended reality space corresponding to the real space based on the effective plane plate set.

Abstract: A method for adjusting an optical switch keyboard and an optical switch keyboard using the adjusting method are provided. The optical switch keyboard has a number of key units. The method includes the following steps. A scan signal is applied to one of a number of scan lines by a control unit at a first scan time point. A light is emitted by a light source according to the scan signal. A light emitted by the light source is detected by a detecting element to generate a detecting electric signal. The detecting electric signal is read by the control unit to obtain a first read signal voltage. When the first read signal voltage is outside the voltage range of the pressed state of the key unit, the period of the scan signal is increased by a first predetermined amount by the control unit to obtain an adjusted scan signal.

Abstract: A method for adjusting an optical switch keyboard and an optical switch keyboard using the adjusting method are provided. The optical switch keyboard has a number of key units. The method includes the following steps. A scan signal is applied to one of a number of scan lines by a control unit at a first scan time point. A light is emitted by a light source according to the scan signal. A light emitted by the light source is detected by a detecting element to generate a detecting electric signal. The detecting electric signal is read by the control unit to obtain a first read signal voltage. When the first read signal voltage is outside the voltage range of the pressed state of the key unit, the period of the scan signal is increased by a first predetermined amount by the control unit to obtain an adjusted scan signal.

Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.