Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped source area having conductivity determining impurities at a heavily doped source concentration and a lightly doped drain area having conductivity determining impurities at a lightly doped drain concentration less than the heavily doped source concentration. A drain conductor directly contacts the lightly doped drain area, and a channel is positioned between the heavily doped source area and the lightly doped drain area. A gate overlies the channel.

Abstract: Device and a method of forming an integrated circuit (IC) that offers protection against ESD in RE applications is disclosed. The device includes a transmission line (TL) coupled to a signal pad. The TL is a short circuited stub that is configured as an ESD protection device and as a band pass filter in dependence of a center frequency of the band pass filter. The TL is configured to pass through a signal in response to a frequency of the signal being within an allowable range of frequencies of the band pass filter. The TL functioning as an ESD protection device is configured to shunt the signal in response to the frequency being outside the allowable range. The IC may include an array of control switches that are operable to change an electrical length L of the TL. The center frequency is tunable by controlling the electrical length L.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a first common line and a second common line. A first electrostatic discharge line is in electrical communication with the first and second common lines. The first electrostatic discharge line includes a first diode and a first clamping device.

Abstract: Integrated circuits with components for protection from electrostatic discharge are provided. An integrated circuit includes a first common line and a second common line. A first electrostatic discharge line is in electrical communication with the first and second common lines. The first electrostatic discharge line includes a first diode and a first clamping device.

Abstract: An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

Abstract: Techniques are described for processing signal information from a high speed communication bus. The techniques include determining spatial regions on an eye by sampling a plurality of time and voltage points to determine a two-dimensional matrix. Then, the points are assigned a numerical value from combined time and voltage functions based upon a distance from eye edges (e.g., minimum setup time requirement and minimum hold time requirement along the time dimension). Sampling to generate the matrix may comprise selecting an initial point, splitting a first margin along a first dimension into equally spaced regions, and then sampling a second margin along a second dimension into equally spaced regions. Determining the points is based on shifting a strobe signal (DQS) position and a data signal (DQ) position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract: A keyboard device includes M driving circuits DC(1)˜DC(M), N transition circuits TC(1)˜TC(N), a control module, M column signal lines C(1)˜C(M), N row signal lines R(1)˜R(N) and M*N key units KU(1,1)˜KU(M,N). The control module performs a scanning process to sequentially scan the M column signal lines C(1)˜C(M) in M scan cycles scan(1)˜scan(M). If the key unit KU(k,x) connected with the k-th column signal line C(k) and the x-th row signal line R(x) is depressed, a scan voltage is transmitted from the k-th column signal line C(k) to the x-th row signal line R(x) through a switch sw(k,x) of the key unit KU(k,x). The transition circuit TC(x) connected with the x-th row signal line R(x) is turned on according to the scan voltage. Consequently, an output voltage Rout(x) from the transition circuit TC(x) has a first voltage level.

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

Abstract: Device and a method of forming an integrated circuit (IC) that offers protection against ESD in RE applications is disclosed. The device includes a transmission line (TL) coupled to a signal pad. The TL is a short circuited stub that is configured as an ESD protection device and as a band pass filter in dependence of a center frequency of the band pass filter. The TL is configured to pass through a signal in response to a frequency of the signal being within an allowable range of frequencies of the band pass filter. The TL functioning as an ESD protection device is configured to shunt the signal in response to the frequency being outside the allowable range. The IC may include an array of control switches that are operable to change an electrical length L of the TL. The center frequency is tunable by controlling the electrical length L.

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract: An ESD device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit. The ESD device is configured to be off during normal operation of the circuit and to turn on in response to an electrostatic discharge on the signal path. Two depletion regions in the device are separated by an isolation well. In response to the electrostatic discharge, the depletion regions modulate (e.g., widen and merge), providing a path for the discharge to the ground of the circuit.

Abstract: An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.

Abstract: A memory interface for a plurality of DRAM devices comprising an input DRAM address matching module includes a local memory comprising a plurality of data entries, wherein the plurality of data entries comprising a plurality of DRAM addresses and a plurality of associated pointers, and wherein the plurality of associated pointers comprise output DRAM addresses, and a matching mechanism coupled to the local memory, wherein the matching mechanism is configured to receive the input DRAM address, wherein the matching mechanism is configured to determine whether the input DRAM address is specified in the plurality of data entries, and when the input DRAM address is specified in the plurality of data entries, the matching mechanism is configured to output an associated pointer associated with the input DRAM address.

Abstract: An image capture method is provided for a portable communication device having a display unit, which real-time displays an image at least including an object to be shot. The method includes sensing a moving acceleration of the portable communication device based on a first gravity-sensing threshold value. A touch focus signal is received so that the portable communication device focuses on one of the objects to be the focus-lock object. Then, according to the touch focus signal, the first gravity-sensing threshold value is changed to a second gravity-sensing threshold value, which is larger than the first gravity-sensing threshold value. The image at least including the focus-lock object is captured.

Abstract: A wireless mouse includes a base having a top surface defining a button region and a non-button region, and a top cover including a cover body that separably covers the top surface of the base. The cover body has an inner surface facing the non-button region of the top surface and an integrally formed groove defining member extending from the inner surface into a space disposed between the cover body and the top surface of the base. The groove defining member cooperates with the inner surface of the cover body to define a positioning groove that is open to the space between the cover body and the top surface of the base into which a wireless receiver is received and releasably retained.

Abstract: A light-emitting keyboard includes a keycap, a frame and a solid-state lighting source. The keycap has a light-entrance portion formed on the periphery thereof, and a touch surface for pressing by user. The keycap is made of light-guiding material and defines a light-guiding path from the light entrance portion to the touch surface. The frame is arranged adjacent to the keycap and surrounds the periphery of the keycap. The frame is made of light-guiding material and forms at least one light-outputting surface. The at least one light-outputting surface is contiguous to the light-entrance portion. The solid-state lighting source is fixed to the frame and emits light from the light-outputting surface into the light-entrance portion by the light-guiding path, and exits from the touch surface of the keycap. The instant disclosure also provides an illuminating structure of the keyboard, and a keycap thereof.

Abstract: A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.

Abstract: A wireless mouse includes a base, a battery fastener and a top cover. The base has a top portion that is formed with a battery container unit. The battery fastener includes a fastener body connected removably with the top portion of the base. The battery fastener further includes a blockade unit extending from the fastener body and disposed directly above the battery container unit so as to prohibit the battery unit from exiting the battery container unit. The top cover is connected removably with the base for covering the battery container unit. When the top cover is connected with the base, the battery fastener is located between the top portion of the base and the top cover.