Patents by Inventor Chien-Hsiun Lee
Chien-Hsiun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130093094Abstract: Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chung Sung, Yu-Chih Liu, Wei-Ting Lin, Chien-Hsiun Lee
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Publication number: 20130095607Abstract: Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chung Sung, Yu-Chih Liu, Wei-Ting Lin, Chien-Hsiun Lee
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Publication number: 20130075139Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Hung-Jen Lin, Chien-Hsiun Lee
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Publication number: 20130056880Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.Type: ApplicationFiled: September 1, 2011Publication date: March 7, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Ding WANG, Chien-Hsiun Lee
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Publication number: 20130009303Abstract: A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.Type: ApplicationFiled: July 7, 2011Publication date: January 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Chun Tsai, Sheng-Yu Wu, Ching-Wen Hsiao, Tin-Hao Kuo, Chen-Shien Chen, Chung-Shi Liu, Chien-Hsiun Lee, Mirng-Ji Lii
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Publication number: 20120319251Abstract: An integrated circuit structure includes a substrate and a metal pad over the substrate. A post-passivation interconnect (PPI) line is connected to the metal pad, wherein the PPI line includes at least a portion over the metal pad. A PPI pad is connected to the PPI line. A polymer layer is over the PPI line and the PPI pad, wherein the polymer layer has a thickness greater than about 30 ?m. An under-bump metallurgy (UBM) extends into an opening in the polymer layer and electrically connected to the PPI pad.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Lawrence Chiang Sheu, Hao-Yi Tsai, Chien-Hsiun Lee
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Patent number: 8334170Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.Type: GrantFiled: June 27, 2008Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dean Wang, Chien-Hsiun Lee, Chen-Shien Chen, Clinton Chao, Mirng-Ji Lii, Tjandra Winata Karta
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Publication number: 20120288998Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.Type: ApplicationFiled: July 20, 2012Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Hsiun Lee, Clinton Chao, Mirng Ji Lii, Tjandra Winata Karta
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Patent number: 8247267Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.Type: GrantFiled: March 11, 2008Date of Patent: August 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Hsiun Lee, Clinton Chao, Mirng Ji Lii, Tjandra Winata Karta
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Patent number: 8232183Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.Type: GrantFiled: May 4, 2007Date of Patent: July 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsiun Lee, Ming-Chung Sung, Clinton Chao, Tjandra Winata Karta
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Patent number: 8174114Abstract: A semiconductor package structure with a heat dissipating stiffener and method of fabricating the same are provided. In one embodiment, the package structure comprises a substrate having a front side and a back side; a semiconductor chip mounted on the front surface of the substrate; a thermally-conductive stiffener mounted over the front surface of the substrate and surrounding the chip, the stiffener having a first portion and a second portion, wherein the first portion is wider than the second portion so as to allow for easy egress of a dispenser into a gap between the chip and the substrate; an underfill layer filled and cured in the gap; and a plurality of solder balls mounted on the back surface of the substrate.Type: GrantFiled: December 15, 2005Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Go. Ltd.Inventors: Chien-Hsiun Lee, Yk Hsiao
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Patent number: 8169076Abstract: An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 ?m. A width of the UBM equals one-half of the pitch plus a value greater than 5 ?m.Type: GrantFiled: August 6, 2009Date of Patent: May 1, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mirng-Ji Lii, Chien-Hsiun Lee, Chen-Hua Yu, Shin-Puu Jeng, Chin-Yu Ku
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Patent number: 8039315Abstract: A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.Type: GrantFiled: July 1, 2010Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Hui Lee, Mirng-Ji Lii, Chien-Hsiun Lee
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Patent number: 7977155Abstract: A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.Type: GrantFiled: May 4, 2007Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsiun Lee, Clinton Chao, Ming-Chung Sung, Tjandra Winata Karta
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Publication number: 20110051378Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.Type: ApplicationFiled: June 11, 2010Publication date: March 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Bo-I Lee, Chien-Hsiun Lee
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Publication number: 20100314756Abstract: An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 ?m. A width of the UBM equals one-half of the pitch plus a value greater than 5 ?m.Type: ApplicationFiled: August 6, 2009Publication date: December 16, 2010Inventors: Mirng-Ji Lii, Chien-Hsiun Lee, Chen-Hua Yu, Shin-Puu Jeng, Chin-Yu Ku
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Patent number: 7851916Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.Type: GrantFiled: March 17, 2005Date of Patent: December 14, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Hui Lee, Mickey Ken, Chien-Hsiun Lee, Szu Wei Lu
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Patent number: 7846769Abstract: A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.Type: GrantFiled: December 16, 2009Date of Patent: December 7, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mirng-Ji Lii, Szu-Wei Lu, Tjandra Winata Karta, Chien-Hsiun Lee
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Patent number: 7842548Abstract: A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps.Type: GrantFiled: April 22, 2008Date of Patent: November 30, 2010Assignee: Taiwan Semconductor Manufacturing Co., Ltd.Inventors: Chien-Hsiun Lee, Chen-Shien Chen, Mirng-Ji Lii, Tjandra Winata Karta
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Patent number: 7838424Abstract: An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die.Type: GrantFiled: July 3, 2007Date of Patent: November 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tjandra Winata Karta, Steven Hsu, Chien-Hsiun Lee, Gene Wu, Jimmy Liang