Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

Abstract: A method and system is disclosed for better packaging semiconductor devices. In one example, a semiconductor device package comprises a package substrate, at least one die with an orientation of <100> placed on the substrate with electrical connections made between the package substrate and the die, and an underfill fillet attaching the die to the substrate with the underfill fillet reaching less than 60% of a thickness of the die on at least one side thereof.

Abstract: Disclosed are novel spacer structures for stacked semiconductor package devices. In addition, methods of manufacturing spacers and stacked semiconductor package devices having such spacers are also disclosed. In one embodiment, a spacer includes a first mounting surface couplable to a longitudinal face of a first substrate, where the first mounting surface has a first surface area. The spacer also includes a second mounting surface substantially parallel to the first mounting surface and located on an opposing side of the spacer from the first mounting surface. Furthermore, the second mounting surface is couplable to a longitudinal face of a second substrate and has a second surface area larger than the first surface area.

Abstract: A method of bonding a conductive wire on copper pad is presented. A passivation layer is formed on a copper pad. The passivation layer has an opening through which at least a portion of the copper pad is exposed. A nickel-copper-phosphorous (Ni—Cu—P) layer is formed on the copper pad by electroless plating. A conductive wire is bonded through the Ni—Cu—P layer and to the copper pad. The Ni—Cu—P layer protects the underline copper pads from oxidation so that a better bonding can be formed between the conductive wire and the copper pad.

Abstract: A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

Abstract: A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

Abstract: A method of manufacturing a semiconductor device and structure thereof. The method includes providing a workpiece, the workpiece having at least one conductive pad partially exposed through an opening in a passivation layer, the passivation layer having a top surface and the opening in the passivation layer having sidewalls. A barrier layer is formed over the at least one conductive pad, wherein the barrier layer lines the sidewalls of the opening in the passivation layer and is disposed over a top portion of the passivation layer proximate the opening. A conductive cap is formed over the barrier layer within the opening in the passivation layer, and the conductive cap is recessed to a height below the top surface of the passivation layer. The conductive cap may be used for testing with a probe or may be used for wire-bonding.