Patents by Inventor Chien-hung Lin

Chien-hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261086
    Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin, Chien-Ting Lin, Chun-Ya Chiu, Chia-Jung Hsu, Chin-Hung Chen
  • Publication number: 20250097389
    Abstract: A projection device includes a casing, a light source module, a first heat sink, a second heat sink and a fan. The casing has a first side cover and a second side cover opposite each other, the first side cover has a first opening, and the second side cover has a second opening. The light source module is configured in the casing to provide an illumination beam. The first heat sink is thermally coupled to the light source module. The second heat sink is thermally coupled to the first heat sink, and the second heat sink is closer to the first side cover than the light source module. The fan has an air outlet surface and a side surface adjacent to each other, and the first heat sink is inclined to the fan and extends to the side surface.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 20, 2025
    Applicant: Qisda Corporation
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu
  • Patent number: 12255156
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Hung Chen, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 12256573
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: March 18, 2025
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Chia-Shuai Chang, Chien-Hung Lin, Wen-Fu Yu, Wei-Li Wang, Bae-Yinn Hwang, Jyun-Huei Jiang
  • Patent number: 12249539
    Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
  • Publication number: 20250069980
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 12237404
    Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Publication number: 20250062153
    Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO, Jian-Hung CHEN, M.C. LIN, C.C. CHIEN, Hsuan LEE, Boris HUANG
  • Patent number: 12225363
    Abstract: A speaker module is adapted to be configured to a wearable device. The speaker module includes an enclosure and a driving unit. The driving unit is used to generate sound. The enclosure contains the driving unit. A sound sum of the sound output from a front opening, a first rear opening and a second rear opening of the enclosure has directivity. The connection vectors and the inverse vector of the connection normal vector defined by these openings are added to form a combined vector. A unit vector of the combination vector and a unit vector of a front normal vector facing outwards of the front opening are added to form a sum vector. The direction of the sum vector is the direction of the sound sum.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: February 11, 2025
    Assignee: HTC Corporation
    Inventors: Sung Jen Wang, Chien-Hung Lin
  • Patent number: 12218227
    Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chia-Hung Chou, Chih-Hsuan Chen, Ping-En Cheng, Hsin-Wen Su, Chien-Chih Lin, Szu-Chi Yang
  • Patent number: 12218023
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20250040275
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped supporting layer. The ring-shaped supporting layer has an inner surrounding surface and an outer surrounding surface that is opposite to the inner surrounding surface. At least one of the inner surrounding surface and the outer surrounding surface has a plurality of round-ended microstructures that are sequentially connected to each other and that surround a sensing region of the sensor chip. An end of each of the round-ended microstructures is a round-ended portion having a radius of less than 1 ?m. The light-permeable layer, the inner surrounding surface of the ring-shaped supporting layer, and the sensor chip jointly define an enclosed space.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 30, 2025
    Inventors: CHIEN-HUNG LIN, JYUN-HUEI JIANG, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG
  • Publication number: 20250039646
    Abstract: An internal radio wave transmission system of building includes a base layer and a transmission layer, with a radio wave transmission channel between the two layers. The radio wave transmission system in a building includes a signal transceiver device, a first reflective plate and a second reflective plate. The signal transceiver device is connected with a telecommunication room, and the signal transceiver device emits and receives radio wave signals. The first reflective plate is disposed in the channel and corresponds to positions of the base layer and the signal transceiver device to receive and guide the radio wave signals. The second reflective plate is disposed in the channel and corresponds to a position of the transmission layer to receive and guide the radio wave signals to terminal equipment located in the transmission layer. The invention ensures the effective transmission of the radio wave signals inside the building.
    Type: Application
    Filed: June 20, 2024
    Publication date: January 30, 2025
    Inventors: TZUU-YAW LU, HERMAN CHUNGHWA RAO, Chun-Chieh KUO, Hua-Pei CHIANG, CHYI-DAR JANG, TSUNG-JEN WANG, CHI-HUNG LIN, WEI-DI HWANG, FANG-CHI YEN, CHIEN-LI HOU
  • Publication number: 20250031404
    Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Min-Hsuan LU, Sheng-Tsung WANG, Huan-Chieh SU, Tzu Pei CHEN, Hao-Heng LIU, Chien-Hung LIN, Chih-Hao WANG
  • Patent number: 12205998
    Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Chien-Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12165867
    Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Lin Chang, Chih-Chien Wang, Chihy-Yuan Cheng, Sz-Fan Chen, Chien-Hung Lin, Chun-Chang Chen, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20240364074
    Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has a photonic crystal structure. The insulating layer is disposed on an upper surface and a sidewall surface of the first platform, and on an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, the active layer, and at least a portion of the first waveguiding layer. The first electrode is on the insulating layer and the second electrode is connected to the outer surface of the substrate and arranged to form an opening for laser output.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: YU-CHEN CHEN, CHIEN-HUNG LIN, BO-TSUN CHOU, CHIH-YUAN WENG, KUO-JUI LIN
  • Publication number: 20240337779
    Abstract: An optical device includes an electronic component, a light-permeable layer, and a ring-shaped adhesive layer that is sandwiched between the electronic component and the light-permeable layer. The ring-shaped adhesive layer surrounds an optical region of the electronic component and includes a plurality of light-weakening slots that are formed on an inner side surface thereof. The light-weakening slots are in a ring-shaped arrangement and surround the optical region. Each of the light-weakening slots has a slot opening having a slot width and a slot bottom spaced apart from the slot opening by a slot depth. A width of each of the light-weakening slots gradually decreases along a direction from the slot opening to the slot bottom, and a ratio of the slot width to the slot depth is within a range from 1:0.86 to 1:11.4, such that each of the light-weakening slots is configured to weaken light irradiated thereon.
    Type: Application
    Filed: November 20, 2023
    Publication date: October 10, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG
  • Publication number: 20240298953
    Abstract: An embodiment of the invention provides an electrocardiography (ECG) signal processing device. The ECG signal processing device includes a first part, a second part and a flexible printed circuit board. The first part may comprise a first electrode and a processing circuit. The second part includes a second electrode. The flexible printed circuit board is coupled to the first part and the second part to fold the first part and the second part. When a closed loop is formed between the first electrode and the second electrode, the processing circuit obtains an ECG signal from the user.
    Type: Application
    Filed: September 11, 2023
    Publication date: September 12, 2024
    Inventors: Chia-Yuan CHANG, Jung-Wen CHANG, Chien-Hung LIN
  • Publication number: 20240290897
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: August 29, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG