Patents by Inventor Chien-hung Lin

Chien-hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250126870
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes a fluorine concentration that decreases from the inner surface and the outer surface towards a center of the first gate spacer. The structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, and the second gate spacer includes a fluorine concentration that decreases from an outer surface towards an inner surface.
    Type: Application
    Filed: October 15, 2023
    Publication date: April 17, 2025
    Inventors: Zheng-Yong LIANG, Wei-Ting YEH, Fu-Ting YEN, Hung-Yu YEN, Chien-Hung LIN, Kuei-Lin CHAN, Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20250097389
    Abstract: A projection device includes a casing, a light source module, a first heat sink, a second heat sink and a fan. The casing has a first side cover and a second side cover opposite each other, the first side cover has a first opening, and the second side cover has a second opening. The light source module is configured in the casing to provide an illumination beam. The first heat sink is thermally coupled to the light source module. The second heat sink is thermally coupled to the first heat sink, and the second heat sink is closer to the first side cover than the light source module. The fan has an air outlet surface and a side surface adjacent to each other, and the first heat sink is inclined to the fan and extends to the side surface.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 20, 2025
    Applicant: Qisda Corporation
    Inventors: Chien-Hung Lin, Tzu-Huan Hsu
  • Patent number: 12256573
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: March 18, 2025
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Chia-Shuai Chang, Chien-Hung Lin, Wen-Fu Yu, Wei-Li Wang, Bae-Yinn Hwang, Jyun-Huei Jiang
  • Publication number: 20250069881
    Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 12225363
    Abstract: A speaker module is adapted to be configured to a wearable device. The speaker module includes an enclosure and a driving unit. The driving unit is used to generate sound. The enclosure contains the driving unit. A sound sum of the sound output from a front opening, a first rear opening and a second rear opening of the enclosure has directivity. The connection vectors and the inverse vector of the connection normal vector defined by these openings are added to form a combined vector. A unit vector of the combination vector and a unit vector of a front normal vector facing outwards of the front opening are added to form a sum vector. The direction of the sum vector is the direction of the sound sum.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: February 11, 2025
    Assignee: HTC Corporation
    Inventors: Sung Jen Wang, Chien-Hung Lin
  • Patent number: 12224108
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Feng-Lung Chien, Tsang-Feng Wu, Yuan Han, Tzu-Chieh Kao, Chien-Hung Lin, Kuang-Lun Lee, Hsiang-Hui Hsu, Shu-Yi Tsui, Kuo-Jui Lee, Kun-Ying Lee, Mao-Chun Chen, Tai-Hsien Yu, Wei-Yu Chen, Yi-Ju Li, Kuei-Yuan Chang, Wei-Chun Li, Ni-Ni Lai, Sheng-Hao Luo, Heng-Sheng Peng, Yueh-Hui Kuan, Hsiu-Chen Lin, Yan-Bing Zhou, Chris T. Burket
  • Publication number: 20250040275
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped supporting layer. The ring-shaped supporting layer has an inner surrounding surface and an outer surrounding surface that is opposite to the inner surrounding surface. At least one of the inner surrounding surface and the outer surrounding surface has a plurality of round-ended microstructures that are sequentially connected to each other and that surround a sensing region of the sensor chip. An end of each of the round-ended microstructures is a round-ended portion having a radius of less than 1 ?m. The light-permeable layer, the inner surrounding surface of the ring-shaped supporting layer, and the sensor chip jointly define an enclosed space.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 30, 2025
    Inventors: CHIEN-HUNG LIN, JYUN-HUEI JIANG, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG
  • Publication number: 20250031404
    Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Min-Hsuan LU, Sheng-Tsung WANG, Huan-Chieh SU, Tzu Pei CHEN, Hao-Heng LIU, Chien-Hung LIN, Chih-Hao WANG
  • Patent number: 12165867
    Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Lin Chang, Chih-Chien Wang, Chihy-Yuan Cheng, Sz-Fan Chen, Chien-Hung Lin, Chun-Chang Chen, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20240364074
    Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has a photonic crystal structure. The insulating layer is disposed on an upper surface and a sidewall surface of the first platform, and on an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, the active layer, and at least a portion of the first waveguiding layer. The first electrode is on the insulating layer and the second electrode is connected to the outer surface of the substrate and arranged to form an opening for laser output.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: YU-CHEN CHEN, CHIEN-HUNG LIN, BO-TSUN CHOU, CHIH-YUAN WENG, KUO-JUI LIN
  • Publication number: 20240337779
    Abstract: An optical device includes an electronic component, a light-permeable layer, and a ring-shaped adhesive layer that is sandwiched between the electronic component and the light-permeable layer. The ring-shaped adhesive layer surrounds an optical region of the electronic component and includes a plurality of light-weakening slots that are formed on an inner side surface thereof. The light-weakening slots are in a ring-shaped arrangement and surround the optical region. Each of the light-weakening slots has a slot opening having a slot width and a slot bottom spaced apart from the slot opening by a slot depth. A width of each of the light-weakening slots gradually decreases along a direction from the slot opening to the slot bottom, and a ratio of the slot width to the slot depth is within a range from 1:0.86 to 1:11.4, such that each of the light-weakening slots is configured to weaken light irradiated thereon.
    Type: Application
    Filed: November 20, 2023
    Publication date: October 10, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG
  • Publication number: 20240298953
    Abstract: An embodiment of the invention provides an electrocardiography (ECG) signal processing device. The ECG signal processing device includes a first part, a second part and a flexible printed circuit board. The first part may comprise a first electrode and a processing circuit. The second part includes a second electrode. The flexible printed circuit board is coupled to the first part and the second part to fold the first part and the second part. When a closed loop is formed between the first electrode and the second electrode, the processing circuit obtains an ECG signal from the user.
    Type: Application
    Filed: September 11, 2023
    Publication date: September 12, 2024
    Inventors: Chia-Yuan CHANG, Jung-Wen CHANG, Chien-Hung LIN
  • Publication number: 20240290897
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: August 29, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG
  • Patent number: 12068376
    Abstract: Integrated semiconductor devices and method of making the integrated semiconductor are disclosed. The integrated semiconductor device may include a first transistor comprising a first gate and at least one first active region, a second transistor comprising a second gate and at least one second active region, wherein the second transistor is spaced a first distance from the first transistor, a dielectric sidewall spacer formed on a gate sidewall of the first transistor and a gate sidewall of the second transistor, a first dielectric layer formed over the first transistor and the second transistor, wherein a thickness of the first dielectric layer is greater than half the first distance, and a patterned metal layer formed on the first dielectric layer and partially covering the second gate.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hung Lin, Tsai-Hao Hung
  • Patent number: 12068575
    Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a light-transmissive conducting layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has multiple holes to form a photonic crystal structure. The insulating layer is over an upper surface and a sidewall surface of the first platform, and over an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, and the active layer. The light-transmissive conducting layer connects to the photonic crystal structure through an aperture of the insulating layer. The first electrode has an opening corresponding to the aperture. The second electrode is under the substrate.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 20, 2024
    Assignee: PHOSERTEK CORPORATION
    Inventors: Yu-Chen Chen, Chien-Hung Lin, Bo-Tsun Chou, Chih-Yuan Weng, Kuo-Jui Lin
  • Publication number: 20240204020
    Abstract: An optical package structure and a method for manufacturing the same are provided. The optical package structure includes an optical element, a bonding structural member, and a light transmittable member. The bonding structural member is bonded to a surface of the optical element. The bonding structural member includes a first bonding layer, a light-absorption layer, and a second bonding layer. The first bonding layer and the second bonding layer are made of an opaque material. The light-absorption layer is disposed between the first bonding layer and the second bonding layer. The light transmittable member is bonded to the bonding structural member and spaced apart from the optical element. The light-absorption layer is configured to absorb light emitted to the bonding structural member.
    Type: Application
    Filed: September 25, 2023
    Publication date: June 20, 2024
    Inventors: CHIEN-HUNG LIN, BAE-YINN HWANG, WEN-FU YU, WEI-LI WANG
  • Publication number: 20240204019
    Abstract: An optical package structure includes a light transmittable member, a bonding structural member, and an optical element. The bonding structural member includes a first bonding layer and a second bonding layer to form a light-scattering structure. The first bonding layer is connected to a bonding surface of the light transmittable member. An inner side of the first bonding layer includes a plurality of first protruded portions. An inner side of the second bonding layer includes a plurality of second protruded portions. The second protruded portions and the first protruded portions are arranged in a staggered manner. The bonding structural member includes the first bonding layer or the light-absorption member. The light-absorption member is filled in concaved portions of the first bonding layer. The optical element is connected to the bonding structural member, and is spaced apart from the light transmittable member.
    Type: Application
    Filed: September 3, 2023
    Publication date: June 20, 2024
    Inventors: CHIEN-HUNG LIN, BAE-YINN HWANG, WEN-FU YU, WEI-LI WANG
  • Publication number: 20240170534
    Abstract: A method for manufacturing a nanosheet semiconductor device includes: forming a liner layer to cover first and second fin structures, each of the fin structures including a stacked structure, a poly gate disposed on the stacked structure, and inner spacers, the stacked structure including sacrificial features covered by the inner spacers, and channel features disposed to alternate with the sacrificial features; forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that interconnects the upper and lower portions and that laterally covers the liner layer; subjecting the upper and lower portions to a directional treatment; and removing the upper and interconnecting portions of the dielectric layer and a portion of the liner layer, to form a liner and a bottom dielectric insulator disposed on the liner.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhi-Chang LIN, Ko-Feng CHEN, Chien-Ning YAO, Chien-Hung LIN
  • Publication number: 20240128291
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
  • Publication number: 20240128233
    Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN