Abstract: Provided is a sensing and adaptation method for exercise. The method is applied to a sensing and adaptation device for exercise and includes the following steps: generating an exercise game and a first resistance setting to an exercise equipment according to a first exercise target data; receiving an exercise interactive data of a user operating the exercise game from the exercise equipment; generating a reaction-time data according to a stage data of the exercise game and the exercise interactive data and generating an operation trajectory data according to the first resistance setting, the stage data and the exercise interactive data; calculating a deviation degree of the operation trajectory data; calculating a second exercise target data according to the deviation degree; generating a second resistance setting and updating the exercise game according to the second exercise target, and transmitting the second resistance setting to the exercise equipment.

Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.

Abstract: A time synchronization method is provided for a time synchronization device, wherein the time synchronization device runs a plurality of precision time protocol (PTP) instances to connect to a plurality of time synchronization domains respectively. The time synchronization method includes determining whether a frequency of a local PTP clock of the time synchronization device is changed; and updating a frequency of a local clock of the time synchronization device with the frequency of the local PTP clock in response to the frequency of the local PTP clock being changed.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A time synchronization method used for a time synchronization device is provided. The time synchronization device runs a plurality of Precision Time Protocol (PTP) instances to connect to a plurality of time synchronization domains through a plurality of ports. The time synchronization method includes selecting a grandmaster (GM) clock from the plurality of time synchronization domains; updating clock information of the grandmaster clock; determining whether each of the plurality of ports is a time receiving port or a time transmitting port according to the grandmaster clock; modifying clock attributes of each of the plurality of PTP instances according to whether the corresponding port is the time receiving port or the time transmitting port; and synchronizing, by the plurality of PTP instances, timings of the plurality of time synchronization domains according to the grandmaster clock.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: A variable resistor and a digital-to-analog converter are provided. The variable resistor includes a main resistor, a plurality of switches, and a plurality of redundancy resistors. The switches are respectively constituted by a plurality of non-volatile memory cells. The switches are coupled to the main resistor. The redundancy resistors are respectively coupled to the main resistor through the switches.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch and a judgment circuit. A first terminal of the control switch is coupled to the control pin. A second terminal of the control switch is coupled to a reference low voltage. The judgment circuit turns on the control switch during a period when the blocking switch is turned off to obtain a sensing current value of a current flowing through the control switch. When the sensing current value is lower than a reference current value, the judgment circuit provides a notification signal for allowing the blocking switch to be turned on.

Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch, a variable resistance circuit, and a judgment circuit. A first terminal of the control switch is coupled to the control pin. The variable resistance circuit is coupled between a second terminal of the control switch and a reference low voltage. The judgment circuit controls the variable resistance circuit to provide a detection resistance value with a minimum value, and turns on the control switch to obtain a sensing voltage value. When the detection resistance value has a maximum value and the sensing voltage value is lower than a reference voltage value, the judgment circuit provides a notification signal.

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Abstract: A projection device includes a casing, a light source module, a first heat sink, a second heat sink and a fan. The casing has a first side cover and a second side cover opposite each other, the first side cover has a first opening, and the second side cover has a second opening. The light source module is configured in the casing to provide an illumination beam. The first heat sink is thermally coupled to the light source module. The second heat sink is thermally coupled to the first heat sink, and the second heat sink is closer to the first side cover than the light source module. The fan has an air outlet surface and a side surface adjacent to each other, and the first heat sink is inclined to the fan and extends to the side surface.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.