Abstract: A character recognition method includes the stages as detailed in the following paragraph. An image is received, wherein the image is one in a plurality of consecutive images. A target object in the image is detected. Object information of the target object is defined according to the area ratio of the target object occupied in the image. Whether the target object in the image is the same as the target object in the previous image is determined according to the object information. Character recognition on the target object is performed to obtain a recognition result. The weighting score of the recognition result is calculated according to the object information and the recognition result. The weighting score of the recognition result of the target object in the consecutive images is accumulated until the weighting score is higher than a preset value, and the recognition result is output.

Abstract: An unmanned ground vehicle (UGV) includes one or more motors configured to drive one or more wheels of the UGV, an obstacle sensor, a memory storing instructions, and a processor coupled to the one or more motors, the obstacle sensor, and the memory. The processor is configured to execute the instructions to cause the UGV to obtain location information of multiple navigation points; calculate a navigation path based on the obtained location information; drive the one or more motors to navigate the UGV along the navigation path; detect, by the obstacle sensor, whether one or more obstacles exist while navigating the UGV, and if detected, determine location information of the one or more obstacles; and if the one or more obstacles are detected by the obstacle sensor, update the navigation path based on determined location information of the one or more obstacles.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

Abstract: A wide-angle lens assembly includes a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth lenses, all of which are orderly arranged from an object side to an image side along an optical axis. The first, fourth, fifth, seventh, and eighth lenses are with refractive power. The second, third, and sixth lenses are with positive refractive power. The wide-angle lens assembly satisfies at least one of the following conditions: 0.8?f/D22?3; 0.025 degrees?1?1/??0.3 degrees?1; 0.03 degrees?1?1/??0.35 degrees?1; 0.5??/??30; wherein f is an effective focal length of the wide-angle lens assembly, D22 is an effective optical diameter of an image side surface of the second lens, ? is a maximum tangent angle of a first cemented surface, and ? is a maximum tangent angle of a second cemented surface.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: A flash memory controller includes a specific buffer and a processor. The specific buffer allocates a cache space. The processor receives a specific host address sent from the host device, reads and loads a corresponding address pointer mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer linker, determines a specific address pointer corresponding to the specific host address from the corresponding address pointer mapping table according to the specific host address, reads and loads a corresponding address mapping table from the flash memory into the cache space according to address information pointed by a specific address pointer corresponding to the specific host address, and finds a specific flash memory address from the corresponding address mapping table according to the specific host address to perform an access operation in response to the found specific flash memory address.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dummy gate structure over the first fin structure and the second fin structure, and removing a portion of the first fin structure and the second fin structure to form a first source/drain (S/D) recess and a second S/D recess. The method includes forming a first bottom layer in the first S/D recess and a second bottom layer in the second S/D recess, and forming a first dielectric liner layer over the first bottom layer. The method includes forming a first top layer over the first dielectric liner layer, and forming a first S/D structure over the first top layer and a second S/D structure over the second bottom layer.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure over the substrate. The package structure also includes a warpage-control element laterally surrounding the chip-containing structure. The warpage-control element has a protruding portions extending into the substrate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.

Abstract: A laser device includes a substrate, a first waveguiding layer, an active layer, a second waveguiding layer, a contact layer, an insulating layer, a first electrode, and a second electrode. The first waveguiding layer, the active layer, the second waveguiding layer, and the contact layer form an epitaxy structure having a first platform and a second platform. The first platform has a photonic crystal structure. The insulating layer is disposed on an upper surface and a sidewall surface of the first platform, and on an upper surface of the second platform. The sidewall surface passes through the contact layer, the second waveguiding layer, the active layer, and at least a portion of the first waveguiding layer. The first electrode is on the insulating layer and the second electrode is connected to the outer surface of the substrate and arranged to form an opening for laser output.