Patents by Inventor Chien-Kang Chou
Chien-Kang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8148822Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.Type: GrantFiled: May 17, 2006Date of Patent: April 3, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen
-
Patent number: 8120181Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: July 30, 2008Date of Patent: February 21, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20110266680Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
-
Publication number: 20110266669Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.Type: ApplicationFiled: July 12, 2011Publication date: November 3, 2011Applicant: MEGICA CORPORATIONInventors: Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo
-
Publication number: 20110233776Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: June 13, 2011Publication date: September 29, 2011Applicant: MEGICA CORPORATIONInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
-
Patent number: 8021918Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: GrantFiled: September 29, 2007Date of Patent: September 20, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Patent number: 8018060Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: January 16, 2008Date of Patent: September 13, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20110215469Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Applicant: Megica CorporationInventors: Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20110215476Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Applicant: Megica CorporationInventors: Jin-Yuan Lee, Chien-Kang Chou, Shih-Hsiung Lin, Hsi-Shan Kuo
-
Patent number: 8013449Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.Type: GrantFiled: June 20, 2008Date of Patent: September 6, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Patent number: 8008775Abstract: A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.Type: GrantFiled: December 20, 2004Date of Patent: August 30, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
-
Publication number: 20110204510Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo
-
Patent number: 8004083Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: GrantFiled: September 29, 2007Date of Patent: August 23, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Patent number: 8004092Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.Type: GrantFiled: June 4, 2008Date of Patent: August 23, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin
-
Patent number: 7989954Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: GrantFiled: September 29, 2007Date of Patent: August 2, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Patent number: 7990037Abstract: The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.Type: GrantFiled: November 27, 2006Date of Patent: August 2, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo
-
Patent number: 7985653Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.Type: GrantFiled: November 24, 2008Date of Patent: July 26, 2011Assignee: Megica CorporationInventors: Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee
-
Patent number: 7977803Abstract: A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.Type: GrantFiled: November 7, 2010Date of Patent: July 12, 2011Assignee: Megica CorporationInventors: Nick Kuo, Chiu-Ming Chou, Chien-Kang Chou, Chu-Fu Lin
-
Patent number: 7969006Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.Type: GrantFiled: September 29, 2007Date of Patent: June 28, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Jin-Yuan Lee, Chien-Kang Chou
-
Patent number: 7964973Abstract: A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.Type: GrantFiled: September 1, 2008Date of Patent: June 21, 2011Assignee: Megica CorporationInventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo