Abstract: The invention provides a method of avoiding peeling on the wafer edge and the mark number. The method uses a design rule to expose the multi-layer on a wafer. The limit and the scope of the exposed distance are taken to ensure the polysilicon layers and the metal layers are covered by the dielectric layer after exposure. The polysilicon layers or the metal layers don't unclothe from the overlarge distance at the exposed dielectric layer, so the next structure formed on the exposed dielectric layer doesn't peeling from contacting with the polysilicon layer or the metal layer. The invention avoids to contaminate the wafer and the machine after the particles forming from peeling.

Abstract: A method for manufacturing shallow trench isolation comprising the steps of providing a substrate, then forming a pad oxide layer over a substrate using a thermal oxidation process. After that, a silicon nitride layer is formed over the pad oxide layer using a low pressure chemical vapor deposition method. Next, using conventional photolithographic and etching processes, the silicon nitride layer is patterned to form an opening exposing the pad oxide layer. In a subsequent step, the pad oxide layer exposed by the opening and the substrate below the opening is etched to form a deep trench. Thereafter, portions of the silicon nitride layer and the pad oxide layer are etched away using hot phosphoric acid solution to expose portions of the substrate. Finally, a liner oxide layer is formed over the interior surface of the trench. The characteristic of this invention includes the formation of a smooth upper trench corners and a liner oxide layer thicker than the pad oxide layer.