Abstract: A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.

Abstract: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasing pad disposed in a stress-releasing area that is at a corner of the integrated circuit die outside the die seal ring, wherein the thermal stress releasing pad is connected to the packaging substrate by using a solder bump, which, in turn, is connected to a dummy heat-spreading metal plate embedded in the packaging substrate so as to form a heat shunting path for reducing thermal stress during temperature cycling test.

Abstract: A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasing pad disposed in a stress-releasing area that is at a corner of the integrated circuit die outside the die seal ring, wherein the thermal stress releasing pad is connected to the packaging substrate by using a solder bump, which, in turn, is connected to a dummy heat-spreading metal plate embedded in the packaging substrate so as to form a heat shunting path for reducing thermal stress during temperature cycling test.

Abstract: A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.

Abstract: A wafer scribe line structure is provided. A plurality of lump patterns is set up to fill the entire scribe line area so that the amount of stress the wafer is subjected to during a dicing process is reduced, thereby reducing the probability of having a delamination at the interface of wafer layers. Moreover, the lump patterns can be formed simultaneously with metal interconnects in a metal interconnect process.

Abstract: A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.

Abstract: A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively.

Abstract: A method of fabricating a system on a chip device. On a substrate having a memory cell region and a peripheral circuit region a gate oxide layer and a polysilicon layer are formed. The peripheral circuit region can further be divided into a logic device region and a hybrid circuit region. A dielectric layer is formed on the peripheral circuit region. A cap layer and a conductive layer are further formed on the polysilicon layer in the memory cell region and on the dielectric layer in the peripheral circuit region. Using the dielectric layer in the peripheral circuit region and the gate oxide layer in the memory cell region as etch stop, the cap layer and the conductive layer in the peripheral circuit region, and the cap layer, the conductive layer and the polysilicon layer are patterned. As a result, at least a gate and a top electrode are formed in the memory cell region and the hybrid circuit region, respectively.

Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area.

Abstract: The present invention provides a method for forming an embedded memory MOS. The method involves first forming a first dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer, followed by the formation of a protective layer on the surface of the semiconductor wafer. Thereafter, a first photolithographic and etching process(PEP) is used to etch the protective layer and the doped polysilicon layer in the memory array area to form a plurality of gates, and to form lightly doped drains(LDD) adjacent to each gate. A silicon nitride layer and a second dielectric layer are formed, followed by their removal in the periphery circuits region.

Abstract: A structure of memory device with thin film transistor is proposed. The structure of the memory device includes a substrate. The substrate has shallow trench isolation structures, a thin film transistor, a memory cell transistor, a memory peripheral transistor, and logic circuit transistor. The shallow trench isolation structures are located in the memory cell region, the logic circuit region, and also on the memory peripheral region to isolate the memory peripheral region from the memory cell region and the logic circuit region. The thin film transistor with a thin film substrate is located above the shallow trench isolation structure at the logic circuit region. A method for fabricating the memory device with thin film transistor is also proposed, where a thin film conductive layer is formed over the substrate at the logic circuit region to serve as the thin film transistor substrate.

Abstract: A structure of memory device with thin film transistor is proposed. The structure of the memory device includes a substrate. The substrate has shallow trench isolation structures, a thin film transistor, a memory cell transistor, a memory peripheral transistor, and logic circuit transistor. The shallow trench isolation structures are located in the memory cell region, the logic circuit region, and also on the memory peripheral region to isolate the memory peripheral region from the memory cell region and the logic circuit region. The thin film transistor with a thin film substrate is located above the shallow trench isolation structure at the logic circuit region. A method for fabricating the memory device with thin film transistor is also proposed, where a thin film conductive layer is formed over the substrate at the logic circuit region to serve as the thin film transistor substrate.

Abstract: The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area.

Abstract: The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of semiconductor wafer. The method of present invention is first to define a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to depose a dielectric layer, a undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a photoresist layer sequentially. Next, a plurality of gate patterns on the memory array area is defined and the protection layer is etched to the surface of the doped polysilicon layer. Then a plurality of gate patterns on the periphery circuit region is defined in and the doped polysilicon layer, the silicide layer and the undoped polysilicon layer are etched to the surface of the dielectric layer so as to form gates of each MOS transistors in the memory array area and periphery circuit region. Finally a spacer and source and drain region are formed around each gate.

Abstract: The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

Abstract: A semiconductor wafer is provided having both a memory array region and a periphery circuit region. A plurality of gate and LDD are formed in the memory array region. Next, a silicon nitride layer and a second dielectric layer are formed on the surface of the semiconductor wafer, and each contact plug is also formed in the second dielectric layer of the memory array region. The second dielectric layer and the silicon nitride layer in the periphery circuit region are then removed, followed by forming each gate, LDD and spacer in the periphery circuit region by way of a photo-etching-process(PEP), ion implantation, and a deposition process. Finally, a source and drain are formed adjacent to each gate in the periphery circuit region. A self-aligned silicide (salicide) process is performed to form a silicide layer on the surface of each contact plug in the memory array region and on the surface of each gate, source and drain in the periphery circuit region.