Abstract: A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.

Abstract: A method of fabricating a contact node. A first dielectric layer is formed on the substrate. A second dielectric layer and a third dielectric layer are formed in sequence over the substrate. A portion of the first dielectric layer, the second dielectric layer, and the third dielectric layer are etched to form a contact opening which exposes a portion of the substrate. A conductive layer is formed in the contact opening. The third dielectric layer is removed to exposes a portion of the conductive layer.

Abstract: A method for forming different patterns using one phase shifting mask. The phase shifting mask has a bit line contact pattern and a node contact pattern thereon. The exposure pattern is changed by using different defocus conditions. In a first defocus situation, the bit line contact pattern and the node contact pattern of the PSM are simultaneously transferred to a photoresist layer. However, in a second defocus situation, only the bit line contact pattern is transferred to the photoresist layer. A phase shifting mask thus can be used in two different photolithography processes.

Abstract: A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

Abstract: An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

Abstract: This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask.

Abstract: A method for reducing the short channel effect of a metal-oxide-semiconductor device by forming a pocket region in a substrate is disclosed, in which the substrate has a channel region under the gate of the device, the channel region has an anti-punch-through region formed thereunder, and a lightly-doped drain region is under the edge portion of the gate. The method includes implanting silicon at a region between the anti-punch-through region and a pre-defined source/drain region to form a point defect region under the lightly-doped drain region, and annealing the substrate such that the dopant in the anti-punch-through region diffuses into the point defect region.

Abstract: A method of forming a bottom electrode of a capacitor in a dynamic random access memory cell. The bottom electrode of the capacitor is formed on a semiconductor wafer, the semiconductor wafer includes a silicon substrate, and a first dielectric layer positioned on the silicon substrate having a contact hole extending down to the silicon substrate. The method includes the following steps: a first polysilicon layer is formed in the contact hole as a conductive plug. A second dielectric layer is then formed on the first dielectric layer. A vertical opening is formed in the second dielectric layer that extends down to the contact hole, and a pillar-shaped second polysilicon layer is formed in the opening, that the bottom end of the second polysilicon layer is electrically connected to the first polysilicon layer in the contact hole.

Abstract: A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A method of reducing resistance of a contact. A semiconductor substrate having at least a conductive lines formed thereon is provided. A self-aligned contact window is formed to expose a part of the substrate. A recess with a ragged surface is formed on the exposed part of substrate within the contact window.

Abstract: A method of fabricating shallow trench isolation structures. A substrate is provided and a masking layer and an oxide layer are formed respectively on the substrate. The masking layer, the oxide layer and the substrate are defined and an opening is formed within the substrate. A portion of masking layer and the oxide layer are removed and an insulating material is later formed to fill with the opening. The masking layer is removed and the shallow trench isolation structure of this invention is therefore achieved.

Abstract: A method of fabricating a self-align-contact is provided. First, a semiconductor substrate is provided on which there are two gates, a source/drain region between the two gates and a first spacer on the sidewalls of each gate. The first spacer is removed. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate. The first dielectric layer is 200-300 .ANG. thick. The second dielectric layer is patterned. The first dielectric layer is anisotropically etched by using the second dielectric layer as a mask to form a self-align-contact opening between the two gates to expose the source/drain region, and to form a second spacer on the sidewalls of the gate. The width of the second spacer is smaller than the width of the first spacer. Therefore, the exposed area of the source/drain region connected the self-align-contact increases.

Abstract: A method for manufacturing local interconnects includes providing a substrate with a gate oxide layer thereover, a first gate electrode and a second gate electrode above the gate oxide layer, spacers on the sidewalls of the gate electrodes, including a first spacer on one sidewall of the first gate electrode and a second spacer on the other sidewall of the first gate electrode. Then, a photoresist layer is applied while keeping the first spacer exposed. Subsequently, the first spacer is removed to expose the sidewall of the first gate electrode. Then, a metal silicide layer is formed over the first gate electrode, the second gate electrode, the one sidewall of the first gate electrode and the substrate. Wet etching is used to remove the first spacer so that local interconnects are automatically formed after the self-aligned silicide processing operation.

Abstract: A method for forming the dielectric layer of a capacitor. A titanium layer and a tantalum pentoxide layer are sequentially formed over a polysilicon lower electrode. A high-temperature treatment is performed so that titanium in the titanium layer and silicon in the polysilicon lower electrode react to form a titanium silicide layer at their interface. Titanium in the titanium layer also reacts with oxygen in the atmosphere to form a titanium oxide layer at its interface with the tantalum pentoxide layer. The titanium silicide layer, the titanium oxide layer and the tantalum pentoxide layer together constitute a composite dielectric layer with a high dielectric constant capable of increasing the capacitance of the capacitor.

Abstract: A method of fabricating a self-align-contact is provided. Two gates are formed on a semiconductor substrate. A first spacer is formed on the sidewalls of the two gates, and a source/drain region is formed between the two gates. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate. The second dielectric layer is patterned. A self-align-contact opening is formed between the two gates by removing the first dielectric layer and the first spacer using the second dielectric layer as a mask. A second spacer is formed on the exposed sidewalls of the gate. The method of forming the second spacer includes forming an insulating layer that is about 200-100 .ANG. thick and anisotropically etching the insulating layer. The width of the second spacer is narrower than the width of the first spacer. A conductor layer is formed in the self-align-contact opening.

Abstract: A bonding-pad structure for integrated circuit is provided. The bonding-pad structure is designed for use in an IC chip constructed on a semiconductor substrate formed with a plurality of circuit components for the purpose of electrical connection to these circuit components. The bonding-pad structure comprises: a first metal-interconnect structure formed over the substrate for electrically interconnecting the various circuit components in the substrate; and a second metal-interconnect structure formed over the substrate within the first metal-interconnect structure, which has an exposed posed surface at a selected location on the bonding side of the IC chip to serve as a bonding pad.

Abstract: A method for manufacturing a shallow trench isolation structure comprising the steps of forming a masking layer over a substrate; then, patterning the masking layer to form an opening; thereafter, forming an oxide layer over the surface of the masking layer and the opening; and, etching back the oxide layer to form oxide spacers on the sidewalls of the masking layer. Subsequently, the substrate is etched downward along the side edges of the oxide spacers to form a trench. Thereafter, the oxide spacers are removed to expose the substrate surface formerly blocked by the oxide spacers. Finally, a liner oxide layer is formed on the trench surface over the substrate. The characteristic of this invention is the formation of a smoother and thicker liner oxide layer. Hence, device current leakage due to subthreshold current and associated kink effect can be avoided.