Abstract: A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node.

Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Abstract: The present invention discloses a multilayer controlling system of data transfer and the method using thereof. The disclosed multilayer controlling system is used for controlling data to transfer from a service operator to pluralities of clients. The system comprises a remote server, at least one intermediate server and pluralities of set-top boxes. The remote server is disposed at the service operator and connects with the intermediate server via a first network interface to take the initiative in transferring the data to the intermediate server. The set-top boxes are disposed at the clients, and the intermediate server connects with the set-top boxes via a second network interface to take the initiative in transferring the date to the set-top boxes. Each of the set-top boxes has a first storage unit, and the data are stored in the first storage unit of each set-top box.

Abstract: A charge pump exhibiting a voltage compensation function is provided. The charge pump includes: a first current generator, a first semiconductor device, a second current generator, a second semiconductor device, and a voltage regulator. The voltage regulator dynamically adjusts a voltage level at the gate of the first or second semiconductor device so as to adjust a first current or a second current outputted to a current output node. In addition, the voltage regulator provides a bias voltage at the current output node when both the first and second semiconductor devices are turned off.

Abstract: A charge pump includes a first current source unit and a second current source unit. The first current source unit is connected between a first voltage terminal and the control node. The second current source unit is connected between the control node and a second voltage terminal. According to a phase comparing signal, the first current source unit provides a first switching current to the control node. The second current source unit includes a first sub-switching current generator, a second sub-switching current generator and a select circuit. According to a voltage level of the phase comparing signal, the first sub-switching current generator generates a first sub-switching current. According to the voltage level of the phase comparing signal, the second sub-switching current generator generates a second sub-switching current. By the select circuit, the first sub-switching current or the second sub-switching current is provided to the control node.

Abstract: A lens displacement device includes a flexible piece, a fixed element and a mobile element. The flexible piece has a support, a flexible part and an oscillation absorber. The flexible part connects to the support and at least one gap exists between the flexible part and the support. The oscillation absorber is installed in the gap between the flexible part and the support. Moreover, the fixed element couples to the support of the flexible piece, and the mobile element couples to the flexible part of the flexible piece. Furthermore, the flexible part of the flexible piece is deformed in shape for providing a restoration force with the mobile element. A manufacturing process of the flexible piece is also disclosed.

Abstract: A portable computer system includes a host, a power storage device and a dock. The power storage device is installed in the host, for sensing current from a first power socket to a first power terminal to generate a first sensing result, and charging a first rechargeable battery according to a first control signal. The dock is capable of connecting to the host by means of insertion, for sensing current from a second power socket to a second power terminal to generate a second sensing result, and charging a second rechargeable battery according to a second control signal. The dock includes a control device for outputting the first control signal and the second control signal according to the first sensing result and the second sensing result, to control charging operations on the first rechargeable battery and the second rechargeable battery.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.

Abstract: A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract: An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract: A power management device for a portable electronic device includes a sensing unit, coupled between a power supply and a system circuit of the portable electronic device, for sensing current outputted from the power supply to the system circuit, to generate a sensing signal, and a control unit, coupled between the sensing unit and a charger module of the portable electronic device, for indicating the charger module to stop charging when the sensing signal indicates that current outputted from the power supply to the system circuit is greater than a predetermined value.

Abstract: A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor.

Abstract: A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor.

Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Abstract: A system for detecting and recording a user's physical parameters, an interactive TV receiver connected to an information network system for receiving physical parameters data detected by the physical parameter scanner and transmitting the data to a rear end server and database through the information network system for enabling a remote user, remote hospital or remote pharmacy to trace patient's physical conditions and to provide the necessary medication services.

Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Abstract: An Ethernet physical layer test system and method, wherein a signal pattern generator is utilized to generate repeatedly a signal pattern frame required by the test items of the Ethernet physical layer according to a transmission procedure of a medium access controller; meanwhile, the signal pattern generator generates a control signal for switching a multiplexer, so as to control the transmission of a signal pattern frame. The Ethernet physical layer receives the signal pattern frame and outputs a test packet to a measurement instrument via a twisted-pair, for testing and analyzing quality of signals output by the Ethernet physical layer. Through the application of this Ethernet physical layer test system and method, the time required for testing the Ethernet physical layer can be effectively reduced, thus simplifying the complexity of an algorithm in testing the Ethernet physical layer.

Abstract: The present invention provides an apparatus for programming functions of a display. The apparatus comprises a memory, a programming device, and a program code checking unit. The memory is for storing a program code. The programming device coupled to the memory is for reading the program code with a predetermined length from the memory. The program code with the predetermined length is part of the program code. The program code checking unit coupled to the programming device is for checking whether the program code with the predetermined length is consistent with a predetermined state, and for selectively generating a control signal. Under control of the control signal, the programming device determines whether to write the program code with the predetermined length into a memory of the display.