Patents by Inventor Chien-Liang Lin

Chien-Liang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8756615
    Abstract: A method and an electronic device for synchronizing information of dual operating systems and a recording medium are provided. The method is used for synchronizing information of a first operating system and a second operating system when an electronic device is switching from a first operating system to a second operating system. First, the second operating system sends an information requesting message to a controller of the electronic device when the first operating system is switched to the second operating system. The controller checks if the first operating system operates in a work mode. If the first operating system operates in the work mode, the controller forwards the information requesting message to the first operating system, so as to obtain the information of the first operating system. Finally, the second system synchronizes the information recorded therein according to the obtained information.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: June 17, 2014
    Assignee: HTC Corporation
    Inventors: Cheng-Hao Chin, Chien-Liang Lin, Shin-Yun Lin
  • Publication number: 20140159211
    Abstract: A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8741784
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8730270
    Abstract: A method for gradually adjusting screen brightness when switching an operating system is provided. The method is used for gradually adjusting the brightness of a screen of an electronic device by a controller thereof when the electronic device is switched from a first operating system to a second operating system. First, an operating system switching signal is received. Then, a first brightness value of the first operating system is obtained. The screen brightness is gradually adjusted from the first brightness value to a predetermined second brightness value. Afterwards, the first operating system is switched to the second operating system, and the screen brightness is further adjusted from the second brightness value back to the first brightness value. Accordingly, a user can sense the switching of the operating system more intuitively and has enough time to get used to the change of the screen brightness and the displayed frame.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: May 20, 2014
    Assignee: HTC Corporation
    Inventor: Chien-Liang Lin
  • Publication number: 20140132853
    Abstract: A capacitive sensing structure is disclosed. The capacitive sensing structure includes a substrate and a plurality of touch units. Each of the touch units includes a first electrode and a second electrode. The first electrode is disposed over a surface of the substrate, and a patterned groove is formed in the first electrode. The patterned groove penetrates the first electrode to form an opening. The second electrode is disposed in the patterned groove and extended out of the first electrode from the opening of the patterned groove. The first electrode is electrically disconnected from the second electrode.
    Type: Application
    Filed: October 3, 2013
    Publication date: May 15, 2014
    Applicant: SONIX Technology Co., Ltd.
    Inventor: Chien-Liang Lin
  • Patent number: 8722501
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chien-Liang Lin, Chien-Ting Lin, Ssu-I Fu, Ying-Tsung Chen
  • Publication number: 20140073111
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Application
    Filed: September 9, 2012
    Publication date: March 13, 2014
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Publication number: 20140010636
    Abstract: A motor base includes a bottom plate and at least one vibration reduction unit. The bottom plate has opposite top and bottom surfaces. A shaft-coupling portion is arranged on the top surface. The at least one vibration reduction unit encloses the shaft-coupling portion. Each of the at least one vibration reduction unit includes at least one protrusion and at least one groove. The at least one protrusion is arranged on one of the top and bottom surfaces. The at least one groove is correspondingly arranged on the other one of the top and bottom surfaces.
    Type: Application
    Filed: March 13, 2013
    Publication date: January 9, 2014
    Applicant: Sunonwealth Electric Machine Industry Co., Ltd.
    Inventors: Kun-Li Hsieh, Chien-Liang Lin
  • Patent number: 8614152
    Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: December 24, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Gin-Chen Huang, Ying-Wei Yen, Yu-Ren Wang
  • Publication number: 20130339780
    Abstract: In a method for processing system events of a computing device, the computing device includes a basic input and output system (BIOS) and a baseboard management controller (BMC). The method allocates revised storage blocks in the BMC, for storing normal system events of the computing device, and a backup storage block in the BMC for storing error system events of the computing device. The method detects a error system event via the BMC, and records the error system event into the backup storage block of the BMC. The method obtains the error system event from the backup storage block of the BMC via the BIOS when the computing device is rebooted, and processes the error system event to reboot the computing device using a normal system event stored in the revised storage blocks of the BMC.
    Type: Application
    Filed: May 15, 2013
    Publication date: December 19, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIEN-LIANG LIN
  • Publication number: 20130334975
    Abstract: Disclosed are a controller and a relevant LED lighting module. A disclosed controller comprises a high-voltage power terminal and a low-voltage power terminal, a major switch circuit, an upward-connection terminal and a downward-connection terminal, and a management circuit. The major switch circuit is coupled between the high-voltage and low-voltage power terminals, and has a driving terminal for coupling to at least one LED. The management circuit is coupled to control the major switch circuit, and configured to communicate with an upstream controller via the upward-connection terminal and to communicate with a downstream controller via the downward-connection terminal. The upward-connection terminal is coupled to the downward-connection terminal of an upstream controller. The downward-connection terminal is coupled to the upward-connection terminal of a downstream controller. The management circuit is capable of operating in one of operation conditions.
    Type: Application
    Filed: October 2, 2012
    Publication date: December 19, 2013
    Applicant: SHAMROCK MICRO DEVICES CORP.
    Inventor: Chien-Liang Lin
  • Publication number: 20130289909
    Abstract: A method of monitoring the working conditions and states of an electronic device sets a first time-interval to read the parameter values of the electronic device. When the electronic device is working normally, the first time-interval is replaced by a second time-interval, which is longer than the first time-interval, to reduce reading frequency, relieve the load on a baseboard management controller (BMC) of the electronic device, and save power.
    Type: Application
    Filed: December 5, 2012
    Publication date: October 31, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHIEN-LIANG LIN
  • Patent number: 8536038
    Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
  • Patent number: 8505417
    Abstract: A socket includes a plurality of protrusions circumferentially disposed around a circular top opening in a top portion of the socket, whereby upon insertion of a driving (or coupling) shaft of a spanner with square head portion into the square hole in the socket, the square head portion of the driving shaft will be respectively biased or thrusted by the protrusions and then smoothly guided or slid through a sloping surface tapered downwardly radially from the circular opening into the square hole for quickly coupling the driving shaft of the spanner with the square hole in the socket. A socket further includes plural bottom protrusions disposed around a circular bottom opening in a bottom portion of the socket, and eighteen faces formed in a hexagonal bottom hole of the socket for helping a quick coupling of a nut or bolt into the bottom hole of the socket.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 13, 2013
    Inventors: Daivd Hui, Chien-Liang Lin
  • Patent number: 8501636
    Abstract: A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Ying-Wei Yen, Kun-Yuan Lo, Chih-Wei Yang
  • Patent number: 8501634
    Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Gin-Chen Huang, Tsuo-Wen Lu, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8482208
    Abstract: Switching mode power supplies (SMPS) and control methods used thereof are disclosed. An exemplifying SMPS is coupled to control an inductive device. The SMPS comprises a voltage divider and a peak controller. The voltage divider comprises a resistor and a controllable resistor connected in series through a connection node. The resistance of the controllable resistor is variable, controlled by a control signal. The voltage divider generates a limiting signal at the connection node based on a line voltage at a line voltage power node. The peak controller controls a peak current flowing through the inductive device according to the limiting signal.
    Type: Grant
    Filed: May 8, 2011
    Date of Patent: July 9, 2013
    Assignee: Shamrock Micro Devices Corp.
    Inventors: Chien-Liang Lin, Sergey Gaitukevich
  • Publication number: 20130171837
    Abstract: A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner.
    Type: Application
    Filed: January 2, 2012
    Publication date: July 4, 2013
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8478978
    Abstract: A system and an electronic device having multiple operating systems and an operating method thereof are provided. The electronic device includes a display and a system having a first operating system, a second operating system, and an embedded controller. The first operating system consumes less power than the second operating system. The embedded controller receives an input signal to switch between the first operating system and the second operating system and display an interface of the switched operating system on a screen of the display. The first operating system and the embedded controller remain in an alive state after the electronic device is turned on, and the second operating system enters a non-working state after a preset idle time.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: July 2, 2013
    Assignee: HTC Corporation
    Inventor: Chien-Liang Lin
  • Patent number: 8470714
    Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 25, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Ssu-I Fu, Chien-Liang Lin, Ying-Tsung Chen, Ted Ming-Lang Guo, Chin-Cheng Chien, Chien-Ting Lin, Wen-Tai Chiang