Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract: Disclosed include switching-mode power supplies and control methods thereof. A disclosed switching-mode power supply is coupled to an input power node and a ground node, comprising a controller, a first inductor, and a bootstrap circuit. The controller is for controlling a power switch coupled to the input power node and a connection node. The controller is powered by the connection node and an operation power node. The first inductor is coupled between the connection node and a discharge node. The bootstrap circuit is coupled between the discharge node, the operation power node and the connection node, to make an operation voltage at the operation power node substantially not less than a discharge voltage at the discharge node. The discharge node is coupled to power an output load.

Abstract: A socket includes a plurality of protrusions circumferentially disposed around a circular top opening in a top portion of the socket, whereby upon insertion of a driving (or coupling) shaft of a spanner with square head portion into the square hole in the socket, the square head portion of the driving shaft will be respectively biased or thrusted by the protrusions and then smoothly guided or slid through a sloping surface tapered downwardly radially from the circular opening into the square hole for quickly coupling the driving shaft of the spanner with the square hole in the socket. A socket further includes plural bottom protrusions disposed around a circular bottom opening in a bottom portion of the socket, and eighteen faces formed in a hexagonal bottom hole of the socket for helping a quick coupling of a nut or bolt into the bottom hole of the socket.

Abstract: A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.

Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.

Abstract: A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.

Abstract: Power switch controllers and methods used therein are disclosed. An exemplifying power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of an inductive device, to generate a trigger signal. The logic controller prevents a power switch connected to the inductive device from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted.

Abstract: A capacitive touch circuit includes a single comparator, a reference voltage control unit, a resistance adjusting unit, a delay unit, and a relaxation oscillation control unit. The comparator has a first input terminal, a second input terminal, and an output terminal. The reference voltage control unit is electrically connected to the second input terminal and includes a high level voltage source, a low level voltage source, and a voltage switching controller. The voltage switching controller electrically connects either the high level voltage source or the low level voltage source to the second input terminal of the single comparator according to an output signal of the single comparator. The relaxation oscillation control unit is electrically connected to the resistance adjusting unit, the delay unit, and the reference voltage control unit.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.

Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.

Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.

Abstract: A method for synchronizing information of dual operating systems is provided. The method is used for synchronizing information of a first operating system and a second operating system when an electronic device is switching from a first operating system to a second operating system. First, the second operating system sends an information requesting message to a controller of the electronic device when the first operating system is switched to the second operating system. The controller checks if the first operating system operates in a work mode. If the first operating system operates in the work mode, the controller forwards the information requesting message to the first operating system, so as to obtain the information of the first operating system. Finally, the second system synchronizes the information recorded therein according to the obtained information.

Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.

Abstract: A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds.

Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.

Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.

Abstract: A method and an electronic device for synchronizing information of dual operating systems and a recording medium are provided. The method is used for synchronizing information of a first operating system and a second operating system when an electronic device is switching from a first operating system to a second operating system. First, the second operating system sends an information requesting message to a controller of the electronic device when the first operating system is switched to the second operating system. The controller checks if the first operating system operates in a work mode. If the first operating system operates in the work mode, the controller forwards the information requesting message to the first operating system, so as to obtain the information of the first operating system. Finally, the second system synchronizes the information recorded therein according to the obtained information.

Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.