Patents by Inventor Chien-Ming Wu
Chien-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978526Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.Type: GrantFiled: March 28, 2022Date of Patent: May 7, 2024Assignee: Skymizer Taiwan Inc.Inventors: Shu-Ming Liu, Kai-Chiang Wu, Chien-Fa Chen, Wen Li Tang
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Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Patent number: 11929561Abstract: An antenna module includes a first antenna radiator including a feeding terminal, a second antenna radiator, a first ground radiator, a second ground radiator and a capacitive element. The second antenna radiator is disposed on one side of the first antenna radiator, and a first gap is formed between a main portion of the second antenna radiator and the first antenna radiator. The first ground radiator is disposed on another side of the first antenna radiator, and a second gap is formed between the first antenna radiator and the first antenna radiator. The second ground radiator is disposed between the second antenna radiator and the first ground radiator, and a third gap is formed between the second ground radiator and a first branch of the second antenna radiator. The capacitive element is disposed on the third gap and connects the second antenna radiator and the second ground radiator.Type: GrantFiled: July 5, 2022Date of Patent: March 12, 2024Assignee: PEGATRON CORPORATIONInventors: I-Shu Lee, Chih-Hung Cho, Hau Yuen Tan, Chien-Yi Wu, Po-Sheng Chen, Chao-Hsu Wu, Yi Chen, Hung-Ming Yu, Chih-Chien Hsieh
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Publication number: 20240079497Abstract: Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Huang, Gao-Ming Wu, Katherine H CHIANG, Chung-Te Lin
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Publication number: 20240072432Abstract: An ultra-wideband antenna device is disposed on a casing of an electronic device. The ultra-wideband antenna device includes radio frequency terminals, a first antenna module, a second antenna module, and a switch module. The radio frequency terminals, the first antenna module and the switch module are located in the casing. The first antenna module is located on a metal frame of the casing, and the first antenna module includes a first antenna. The second antenna module includes a second antenna, a third antenna, and a fourth antenna. The switch module is connected between the radio frequency terminals and the first antenna module. When the switch module turns on one of the radio frequency terminals and the first antenna for distance measurement, the switch module selectively turns on at least one of the second antenna, the third antenna, or the fourth antenna.Type: ApplicationFiled: March 28, 2023Publication date: February 29, 2024Inventors: Yu-Ching WU, Chien-Ming HSU
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Patent number: 11916146Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: GrantFiled: April 11, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Publication number: 20230421165Abstract: The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.Type: ApplicationFiled: June 20, 2023Publication date: December 28, 2023Inventors: WEI-JYUN WANG, KAI-YIN LIU, SHIH-HSIUNG HUANG, CHIEN-MING WU
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Patent number: 11588457Abstract: An analog front-end circuit capable of dynamically adjusting gain includes a programmable gain amplifier (PGA) circuit, a sensor, a calculation circuit, a gain coarse control circuit and a gain fine control circuit. The PGA circuit includes an amplifier, a gain coarse adjustment circuit and a gain fine adjustment circuit. The gain coarse adjustment circuit is controlled by a coarse control signal, and a gain is adjusted in a coarse step according to an initial gain. The gain fine adjustment circuit is controlled by a fine control signal in a data mode, and the gain is adjusted in a fine step. The calculation circuit calculates a primary gain adjustment and a secondary gain adjustment. The gain coarse control circuit generates the coarse control signal according to the primary gain adjustment, and the gain fine control circuit generates the fine control signal according to the secondary gain adjustment.Type: GrantFiled: September 6, 2021Date of Patent: February 21, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chien-Ming Wu, Chung-Ming Tseng
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Publication number: 20220415875Abstract: The present invention provides an ESD protection circuit including a control circuit, a first transistor, a filter and a second transistor. The control circuit is configured to detect a level of a supply voltage to generate a control signal. The first transistor is coupled between the supply voltage and a ground voltage, and is used to refer to the control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage. The filter is configured to filter the control signal to generate a filtered control signal. The second transistor is coupled between the supply voltage and the ground voltage, and is used to refer to the filtered control signal to determine whether to be enabled as a discharging path for the supply voltage to discharge current to the ground voltage.Type: ApplicationFiled: April 25, 2022Publication date: December 29, 2022Applicant: Realtek Semiconductor Corp.Inventor: Chien-Ming Wu
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Patent number: 11496145Abstract: A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.Type: GrantFiled: August 12, 2021Date of Patent: November 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shih-Hsiung Huang, Pan Zhang, Kai-Yin Liu, Chien-Ming Wu
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Publication number: 20220304614Abstract: The present invention provides an electroencephalogram measurement structure formed by an ear-hanging structure and a second circuit board. The ear-hanging structure includes a body. An ear-hanging member is disposed at the extension of the body. The body can be worn on the ear via the ear-hanging member. In addition, a first reference electrode and a second reference electrode are disposed on the body and coupled to a first circuit board. The first circuit board is coupled to an electrical jack; the second circuit board is coupled to the electrical jack via an electrical plug. Thereby, the electroencephalogram measurement can be performed simply by wearing the ear-hanging member on the ear of the person under test. Hence, the problems of complicated wiring and inconvenience in wearing can be solved concurrently.Type: ApplicationFiled: June 3, 2021Publication date: September 29, 2022Inventors: CHUN-MING HUANG, CHEN-CHIA CHEN, GANG-NENG SUNG, CHIEN-MING WU
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Patent number: 11418206Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.Type: GrantFiled: May 28, 2021Date of Patent: August 16, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Shih-Hsiung Huang, Ying-Cheng Wu, Chien-Ming Wu, Kai-Yin Liu
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Publication number: 20220231646Abstract: An analog front-end circuit capable of dynamically adjusting gain includes a programmable gain amplifier (PGA) circuit, a sensor, a calculation circuit, a gain coarse control circuit and a gain fine control circuit. The PGA circuit includes an amplifier, a gain coarse adjustment circuit and a gain fine adjustment circuit. The gain coarse adjustment circuit is controlled by a coarse control signal, and a gain is adjusted in a coarse step according to an initial gain. The gain fine adjustment circuit is controlled by a fine control signal in a data mode, and the gain is adjusted in a fine step. The calculation circuit calculates a primary gain adjustment and a secondary gain adjustment. The gain coarse control circuit generates the coarse control signal according to the primary gain adjustment, and the gain fine control circuit generates the fine control signal according to the secondary gain adjustment.Type: ApplicationFiled: September 6, 2021Publication date: July 21, 2022Inventors: CHIEN-MING WU, CHUNG-MING TSENG
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Patent number: 11394392Abstract: A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.Type: GrantFiled: May 28, 2021Date of Patent: July 19, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Ming Wu, Shih-Hsiung Huang
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Publication number: 20220140836Abstract: A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.Type: ApplicationFiled: August 12, 2021Publication date: May 5, 2022Inventors: SHIH-HSIUNG HUANG, PAN ZHANG, KAI-YIN LIU, CHIEN-MING WU
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Patent number: 11268845Abstract: A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.Type: GrantFiled: May 28, 2020Date of Patent: March 8, 2022Assignee: National Applied Research LaboratoriesInventors: Chun-Ming Huang, Chen-Chia Chen, Chih-Hsing Lin, Chien-Ming Wu
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Publication number: 20220069831Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.Type: ApplicationFiled: May 28, 2021Publication date: March 3, 2022Inventors: SHIH-HSIUNG HUANG, YING-CHENG WU, CHIEN-MING WU, KAI-YIN LIU
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Publication number: 20220052705Abstract: A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.Type: ApplicationFiled: May 28, 2021Publication date: February 17, 2022Inventors: CHIEN-MING WU, SHIH-HSIUNG HUANG
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Patent number: D1024932Type: GrantFiled: March 10, 2022Date of Patent: April 30, 2024Assignee: WALSIN LIHWA CORPORATIONInventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin