Patents by Inventor Chien-Ming Wu
Chien-Ming Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220140836Abstract: A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.Type: ApplicationFiled: August 12, 2021Publication date: May 5, 2022Inventors: SHIH-HSIUNG HUANG, PAN ZHANG, KAI-YIN LIU, CHIEN-MING WU
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Patent number: 11268845Abstract: A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.Type: GrantFiled: May 28, 2020Date of Patent: March 8, 2022Assignee: National Applied Research LaboratoriesInventors: Chun-Ming Huang, Chen-Chia Chen, Chih-Hsing Lin, Chien-Ming Wu
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Publication number: 20220069831Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.Type: ApplicationFiled: May 28, 2021Publication date: March 3, 2022Inventors: SHIH-HSIUNG HUANG, YING-CHENG WU, CHIEN-MING WU, KAI-YIN LIU
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Publication number: 20220052705Abstract: A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.Type: ApplicationFiled: May 28, 2021Publication date: February 17, 2022Inventors: CHIEN-MING WU, SHIH-HSIUNG HUANG
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Patent number: 11245435Abstract: An echo cancellation circuit is coupled to a receiving circuit and a transmitting circuit of an electronic device, and the transmitting circuit includes an output transistor. The echo cancellation circuit includes first and second transistors, first and second resistor-capacitor networks (RC networks), and first and second resistors. The first transistor has a first gate, a first drain and a first source. The second transistor has a second gate, a second drain and a second source. The first drain and the second drain are coupled to the receiving circuit. The first RC network is coupled between the gate of the output transistor and the first gate. The second RC network is coupled between the first gate and the second gate. The first resistor is coupled between the first source and a reference voltage. The second resistor is coupled between the second source and the reference voltage.Type: GrantFiled: August 14, 2020Date of Patent: February 8, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Ming Wu, Chia-Lin Chang
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Patent number: 11133961Abstract: The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.Type: GrantFiled: January 13, 2021Date of Patent: September 28, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Ming Wu, Chung-Ming Tseng
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Patent number: 11128272Abstract: Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.Type: GrantFiled: May 31, 2019Date of Patent: September 21, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Chien-Ming Wu
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Publication number: 20210218602Abstract: The present disclosure discloses a communication apparatus including a receiver circuit and a transmitter circuit having a signal processing circuit and a DAC circuit having a primary conversion circuit and a first hybrid conversion circuit. The primary conversion circuit converts and transmits a transmission signal from the signal processing circuit to a signal transmission path. The first hybrid conversion circuit converts the transmission signal to a first receiver resistor to generate a voltage drop. The receiver circuit receives a first actual receiving signal through the signal transmission path and the first receiver resistor. The primary conversion circuit operates according to a first current including a first and a second part currents and the first hybrid conversion circuit operates according to a second current. The first part current does not change according to a resistive change. The second part current and the second current change according to the resistive change.Type: ApplicationFiled: January 13, 2021Publication date: July 15, 2021Inventors: CHIEN-MING WU, CHUNG-MING TSENG
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Publication number: 20210152213Abstract: An echo cancellation circuit is coupled to a receiving circuit and a transmitting circuit of an electronic device, and the transmitting circuit includes an output transistor. The echo cancellation circuit includes first and second transistors, first and second resistor-capacitor networks (RC networks), and first and second resistors. The first transistor has a first gate, a first drain and a first source. The second transistor has a second gate, a second drain and a second source. The first drain and the second drain are coupled to the receiving circuit. The first RC network is coupled between the gate of the output transistor and the first gate. The second RC network is coupled between the first gate and the second gate. The first resistor is coupled between the first source and a reference voltage. The second resistor is coupled between the second source and the reference voltage.Type: ApplicationFiled: August 14, 2020Publication date: May 20, 2021Inventors: CHIEN-MING WU, CHIA-LIN CHANG
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Publication number: 20210063229Abstract: A liquid level monitoring system includes: a hardware unit with a tube to extend through a surface of a liquid; a processor unit generating control signals that respectively correspond to target frequencies; a sound generator unit generating, respectively based on the control signals, incident sound waves that transmit in the tube and that are reflected by the surface of the liquid to respectively form reflected sound waves; and a sensor unit for sensing the reflected sound waves to respectively generate feedback signals. The processor unit determines a maximum amplitude frequency based on the feedback signals, and calculates a level of the surface of the liquid based on the maximum amplitude frequency and a length of the tube.Type: ApplicationFiled: May 28, 2020Publication date: March 4, 2021Inventors: CHUN-MING HUANG, CHEN-CHIA CHEN, CHIH-HSING LIN, CHIEN-MING WU
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Patent number: 10931101Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.Type: GrantFiled: January 24, 2018Date of Patent: February 23, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Ming Wu, Jian-Ru Lin, Liang-Huan Lei, Cheng-Pang Chan
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Publication number: 20200403501Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.Type: ApplicationFiled: September 24, 2019Publication date: December 24, 2020Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Chien-Ming Wu, Shih-Hsiung Huang, Liang-Huan Lei
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Patent number: 10873256Abstract: A charge-pump boosting is provided. A first resistor is connected to a first storage capacitor and receives a reference voltage, and a second resistor is connected to a second storage capacitor and receives the reference voltage. A first rectifying device is connected to the first storage capacitor and a voltage output. A first clock signal and the reference voltage are used to charge the first storage capacitor, and the first clock signal is used to selectively turn on the first rectifying device to charge the voltage output by the first storage capacitor. The second rectifying device is connected to the second storage capacitor and the voltage output. A second clock signal and the reference voltage are used to charge the second storage capacitor, and the second clock signal is used to selectively turn on the second rectifying device to charge the voltage output by the second storage capacitor.Type: GrantFiled: September 24, 2019Date of Patent: December 22, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chien-Ming Wu, Shih-Hsiung Huang, Liang-Huan Lei
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Patent number: 10700516Abstract: The present invention discloses an electrostatic discharge (ESD) protection circuit including: a first terminal configured to provide a first voltage having a first value in a normal mode; a second terminal configured to provide a second voltage having a second value in the normal mode; a detection circuit configured to provide a detection voltage according to the first and second voltages; and a protection circuit configured to operate in one of the normal mode and an ESD mode according to the detection voltage. When the difference between a value of the detection voltage and an average of the first and second values reaches a predetermined threshold, the protection circuit enters the ESD mode from the normal mode, and thereby has a first path between the first terminal and a grounding terminal and/or a second path between the second terminal and the grounding terminal be conductive for discharging abnormal energy.Type: GrantFiled: February 12, 2018Date of Patent: June 30, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Chien-Ming Wu
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Patent number: 10615814Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.Type: GrantFiled: May 31, 2019Date of Patent: April 7, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chien-Ming Wu, Liang-Huan Lei, Shih-Hsiung Huang
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Patent number: 10608429Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.Type: GrantFiled: March 31, 2017Date of Patent: March 31, 2020Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Tay-Her Tsaur, Cheng-Cheng Yen, Chien-Ming Wu, Cheng-Pang Chan
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Publication number: 20200091924Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.Type: ApplicationFiled: May 31, 2019Publication date: March 19, 2020Inventors: CHIEN-MING WU, LIANG-HUAN LEI, SHIH-HSIUNG HUANG
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Publication number: 20200059211Abstract: Disclosed are a dual-path analog-front-end (AFE) circuit and a dual-path signal receiver characterized by high linearity. The dual-path AFE circuit includes a first reception circuit, a second reception circuit and a multiplexer. The first reception circuit is configured to generate a first analog input signal according to a reception signal in a first mode and configured to be coupled to a first constant-voltage terminal via a first switch circuit in a second mode. The second reception circuit is configured to generate a second analog input signal according to the reception signal in the second mode and configured to be coupled to a second constant-voltage terminal via a second switch circuit in the first mode. The multiplexer is configured to output the first analog input signal in the first mode and output the second analog input signal in the second mode.Type: ApplicationFiled: May 31, 2019Publication date: February 20, 2020Inventor: CHIEN-MING WU
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Patent number: 10536160Abstract: A pipelined analog-to-digital converter includes: a first switched capacitor network, a first digital-to-analog converter, a second switched capacitor network, a second digital-to-analog converter, and an operational amplifier. The outputs from the first switched capacitor network and the first digital-to-analog converter form a first subtraction signal. The outputs from the second switched capacitor network and the second digital-to-analog converter form a second subtraction signal. The operational amplifier is arranged to operably generate an output signal based on the first subtraction signal or the second subtraction signal, and to operably switch coupling relationship of multiple candidate capacitors of the operational amplifier based on the magnitude of an input signal of a prior stage circuit, so that only a portion of the multiple candidate capacitors could be participated in the generation of the output signal at a time.Type: GrantFiled: October 12, 2018Date of Patent: January 14, 2020Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chih-Lung Chen, Shih-Hsiung Huang, Chien-Ming Wu, Jie-Fan Lai
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Patent number: D910009Type: GrantFiled: September 25, 2019Date of Patent: February 9, 2021Assignee: QUANTA COMPUTER INC.Inventors: Chien-Ming Wu, Gwo-Chyuan Chen, Chi-Jen Yu