Abstract: A method of using non-contrast magnetic resonance angiography (NC-MRA) to generate pelvic veins images and measure rate of blood flow includes the ordered steps of: (a) performing a non-contrast magnetic resonance scan in cooperation with an electrocardiogram monitor and a respiration monitor; (b) obtaining two-dimensional images of kidney veins, lower cavity veins, common iliac veins, and external iliac veins using use balanced turbo field echo wave sequence; (c) obtaining three-dimensional images of common cardinal veins of the abdominal cavity using fast spin-echo short tau inversion recovery wave sequence and using sample signals from the electrocardiogram monitor during myocardial contractility; and (d) using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.

Abstract: A docking station includes a network interface controller, a processor, and an output interface controller. The processor is connected to the network interface controller and the output interface controller. The network interface controller receives an operation instruction from an external control device and correspondingly translates the instruction into a communication protocol message. The processor correspondingly writes the communication protocol message into the memory of the processor to update the firmware of the docking station; or the processor correspondingly transmits the communication protocol message to the output interface controller, so that the output interface controller converts the communication protocol message into a display setting instruction and transmits the display setting instruction to display device so as to adjust display parameter of the display device.

Abstract: A media docking device is provided and includes an input module, an output module, and a process module. The input module is electrically connected to a media source device. The output module is electrically connected to multiple media playing devices and obtains device data from the media playing devices. The process module transmits the device data and screen numbers to the media source device through the input module. When determining to perform a display switch procedure, the process module modifies the device data and the screen numbers, and transmits the modified device data and the modified screen numbers to the media source device through the input module. The process module also transmits media data from the media source device to the corresponding media playing device.

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Abstract: A chiller system provides cooling for a semiconductor fabrication facility. The chiller system includes a control system. The control system utilizes one or more analysis models trained with a machine learning process to intelligently assist in reducing the power consumption and enhancing the efficiency of the chiller system.

Abstract: An automated transport vehicle for transporting an article includes a carrying seat, a mechanical arm and a holding mechanism. The holding mechanism includes at least one first positioning post and at least one second positioning post and, when the holding mechanism holds the article, the first positioning post is in contact with a side surface of the article, and the second positioning post is in contact with a bottom surface of the article.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a plurality of ports, a magnetic field sensor, a magnetic port cover, and a processor. A subset of ports of the plurality of ports are deactivated and covered with the magnetic port cover. The magnetic field sensor is coupled to each one of the plurality of ports. The processor is communicatively coupled to the magnetic field sensor. The processor is to detect removal of the magnetic port cover from a deactivated port of the subset of ports that are deactivated via a signal from the magnetic field sensor of the deactivated port and generate notification in response to the magnetic port cover being removed to notify a user to replace the magnetic port cover on the deactivated port.

Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.

Abstract: An image identification method is provided, including: storing at least one normal state image of at least one test object; an automatic codec receiving the at least one normal state image to become a trained automatic codec; at least one camera device capturing at least one state image of the at least one test object; a computer device receiving the at least one state image, and the trained automatic codec performing feature extraction and reconstruction on the at least one state image to generate at least one reconstructed state image; and the computer device comparing the at least one state image and the at least one reconstructed state image, and determining whether the at least one state image is a normal state image. The present invention also provides an image identification system.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Abstract: Techniques pertaining to low-power enhanced multi-link single radio (EMLSR) listen in wireless communications are described. A first multi-link device (MLD) reduces power consumption while supporting a latency-sensitive application by performing certain operations. The first MLD first listens at a lower power in a narrower bandwidth to receive an initial physical-layer protocol data unit (PPDU) from a second MLD as part of a frame exchange. In response to receiving the initial PPDU, the first MLD switches from the narrower bandwidth to a wider bandwidth to complete the frame exchange with the second MLD in the wider bandwidth. In reducing the power consumption, the first MLD reduces its power consumption to the lower power when operating in the narrower bandwidth compared to a higher power used by the first MLD when operating in the wider bandwidth.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

Abstract: A walker is provided. The walker includes a walker body, a handle unit, a first wheel unit and a second wheel unit. The handle unit is connected to the walker body. The first wheel unit is connected to the walker body. The second wheel unit is connected to the walker body. In an auxiliary mode, a first gap is formed between the first wheel unit and the second wheel unit. In a driving mode, a second gap is formed between the first wheel unit and the second wheel unit. The first gap is smaller than the second gap.