Abstract: An electronic device and its touch module are provided. The touch module includes a touch area, a detecting device, and a touch position determining device. The touch area is formed on a case of the electronic device, wherein the touch area includes a plurality of holes; each of the holes can allow light to pass through it when it is not covered by an external object, but cannot allow light to pass through it when it is covered by an external object. The detecting device is positioned under the touch area for detecting whether each hole can allow light to pass through it to determine whether each hole is covered by an external object. The touch position determining device is connected to the detecting device for determining the touch position of the external object according to whether each hole is covered or not.

Abstract: The present invention relates to a transfer printing method and a system using the method for printing images on a workpiece with supercritical fluid. The method includes disposing the workpiece inside the first mold and disposing a transfer film above the workpiece, closing the first mold with a second mold and injecting pressured gas, whose pressure is greater than a critical pressure, into the first mold and the second mold, ensuring a temperature of the pressured gas being greater than a critical temperature so as to convert into supercritical fluid, softening the transfer film with the supercritical fluid, transferring an adhesive layer, a print layer and a hardening layer of the transfer film onto the workpiece, and opening the first mold and the second mold to take out the workpiece.

Abstract: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

Abstract: The present invention provides a method for the oxidation of Hg0 in coal fired flue gas to form Hg2+ which is absorbed by the scrubber solution in wet-FGD or SDA, or adsorbed by the fly ash and subsequently removed from the flue stack with ESP and FF, and/or any other means as are known in the art for SOx, NOx and particulate removals. The addition of a second flue gas stream having a halogen and fly ash therein simultaneously with said hydrogen halogen or interhalogens into a coal fired flue gas further increases the oxidation of Hg0 to Hg2+.

Abstract: A method for making Mg(magnesium)-based intermetallic compound uses a thermal process during a melting process to produce largely the Mg-based intermetallic compound. The vapor pressure of Mg is high, thereby Mg is prone to be vaporized from a melt and a wrought solid alloy in the melting process of high temperature, for purifying the wrought Mg-based intermetallic compound. The method may simplify the process and devices for making the Mg-based intermetallic compound, and produce efficiently a larger of high purity Mg-based intermetallic compound.

Abstract: The invention discloses a testing system and method suitable for determining the connection state of an electronic component in an electronic device assembly. In an embodiment, the testing system comprises a signal sensing unit configured to provide a sensed signal induced by capacitive coupling in response to the output of a testing signal passing through a tested pin, a signal processor unit configured to filter and over-sample the sensed signal to obtain a digital signal, and an analyzer unit configured to compute the digital signal for determining a connection state of the test pin.

Abstract: A method for making Mg(magnesium)-based intermetallic compound uses a thermal process during a melting process to produce largely the Mg-based intermetallic compound. The vapor pressure of Mg is high, thereby Mg is prone to be vaporized from a melt and a wrought solid alloy in the melting process of high temperature, for purifying the wrought Mg-based intermetallic compound. The method may simplify the process and devices for making the Mg-based intermetallic compound, and produce efficiently a larger of high purity Mg-based intermetallic compound.

Abstract: The invention discloses a testing system and method suitable for determining the connection state of an electronic component in an electronic device assembly. In an embodiment, the testing system comprises a signal sensing unit configured to provide a sensed signal induced by capacitive coupling in response to the output of a testing signal passing through a tested pin, a signal processor unit configured to filter and over-sample the sensed signal to obtain a digital signal, and an analyzer unit configured to compute the digital signal for determining a connection state of the test pin.

Abstract: A zirconia sol having zirconia crystals with an average primary particle size less than 20 nm is provided, wherein more than 90% of the zirconia crystals exist in the form of tetragonal and cubic crystal lattice structures. The zirconia sol has a transmittance more than 70% when the amount of the zirconia crystals in the zirconia sol is about 20 wt %.

Abstract: Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elements and peripheral circuitry and results in a reduction in pitch.

Abstract: A semiconductor processes is described. A substrate having trench isolation structures and dummy trench isolation structures thereon is provided. Gate structures and dummy gate structures are simultaneously formed on the substrate. Spacers are formed on the sidewalls of the gate structures and the dummy gate structures. A patterned blocking layer is formed covering the dummy gate structures and the substrate between the dummy trench isolation structures. Thereafter, a salicide layer is formed on exposed surfaces of the gate structures and the substrate.

Abstract: A zirconia sol having zirconia crystals with an average primary particle size less than 20 nm is provided, wherein more than 90% of thezirconia crystals exist in the form of tetragonal and cubic crystal lattice structures. The zirconia sol has a transmittance more than 70% when the amount of the zirconia crystals in the zirconia sol is about 20 wt %.

Abstract: A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides.

Abstract: Nonvolatile memory devices, such as NROM devices that have an oxide-nitride-oxide (ONO) layer beneath at least one word line structure, and methods for making same, are disclosed. The ONO layer is formed on a substrate, followed by a patterned photoresist layer being formed on the ONO layer. The patterned photoresist layer then serves as an implanting mask to form at least one bit line in the substrate, followed by a material layer being formed on the substrate. The material layer is planarized until the photoresist layer is exposed, and the photoresist layer is then removed. A polymer layer is formed, using a dielectric resolution enhancement coating technique, on exposed surfaces of the material layer, with the polymer layer serving as an etching mask to define the top oxide layer and the nitride layer of the ONO layer. The polymer layer and the material layer are then removed.

Abstract: A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer.

Abstract: Nonvolatile memory devices, such as NROM devices that have an oxide-nitride-oxide (ONO) layer beneath at least one word line structure, and methods for making same, are disclosed. The ONO layer is formed on a substrate, followed by a patterned photoresist layer being formed on the ONO layer. The patterned photoresist layer then serves as an implanting mask to form at least one bit line in the substrate, followed by a material layer being formed on the substrate. The material layer is planarized until the photoresist layer is exposed, and the photoresist layer is then removed. A polymer layer is formed, using a dielectric resolution enhancement coating technique, on exposed surfaces of the material layer, with the polymer layer serving as an etching mask to define the top oxide layer and the nitride layer of the ONO layer. The polymer layer and the material layer are then removed.

Abstract: The present invention provides a method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer.

Abstract: This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The present invention uses the way in different etching rates to etch oxide and nitride. When begin the etching process to fabricating the electrically insulating layer, the etching rate of oxide is higher than the etching rate of nitride. When the oxide layer contacts with the ending point which is situated between the oxide layer and the nitride layer or the nitride oxide layer, the etching rate of nitride is higher than the etching rate of oxide to form the flatter surface of the electrically insulating layer.

Abstract: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Abstract: A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides.