Patents by Inventor Chien-Wei Wang
Chien-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250138428Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.Type: ApplicationFiled: January 6, 2025Publication date: May 1, 2025Inventors: Chien-Wei WANG, Wei-Han LAI, Ching-Yu CHANG
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Patent number: 12189296Abstract: Resist rinse solutions and corresponding lithography techniques are disclosed herein. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.Type: GrantFiled: August 30, 2021Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Wei Wang, Wei-Han Lai, Ching-Yu Chang
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Publication number: 20240291949Abstract: A projector and a control method thereof are provided. The projector includes a sensor and a processor coupled to the sensor. The control method of a projector includes: measuring a distance between the sensor and an object through a sensor; and turning on or turning off a projector according to the distance and a threshold.Type: ApplicationFiled: February 22, 2024Publication date: August 29, 2024Applicant: Coretronic CorporationInventors: Chien-Wei Wang, Chih-Lin Wang
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Publication number: 20240222965Abstract: A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Ching-Ho LI, Chun-Chih CHEN, Kai-Chieh HSU, Chien-Wei WANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU, Gong-Kai LIN, Li-Fan CHEN
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Patent number: 12019375Abstract: Materials directed to a photosensitive material and a method of performing a lithography process using the photosensitive material are described. A semiconductor substrate is provided. A first layer including a floating additive is formed over the semiconductor substrate. A second layer including an additive component having a metal cation is formed over the first layer. One or more bonds are formed to bond the metal cation and one or more anions. Each of the one or more anions is one of a protecting group and a polymer chain bonding component. The polymer chain bonding component is bonded to a polymer chain of the layer. The second layer is exposed to a radiation beam.Type: GrantFiled: December 9, 2019Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: An-Ren Zi, Ching-Yu Chang, Chien-Wei Wang
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Patent number: 11940828Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.Type: GrantFiled: August 17, 2022Date of Patent: March 26, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
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Publication number: 20240061455Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Yeh-Ning JOU, Ching-Ho LI, Kai-Chieh HSU, Chun-Chih CHEN, Chien-Wei WANG, Gong-Kai LIN, Li-Fan CHEN
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Publication number: 20230359124Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Inventors: Jing Hong Huang, Chien-Wei Wang, Shang-Wern Chang, Ching-Yu Chang
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Patent number: 11809080Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.Type: GrantFiled: July 29, 2022Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Han Lai, Chin-Hsiang Lin, Chien-Wei Wang
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Patent number: 11703766Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.Type: GrantFiled: July 25, 2022Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jing Hong Huang, Chien-Wei Wang, Shang-Wern Chang, Ching-Yu Chang
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Publication number: 20220382156Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Inventors: Wei-Han Lai, Chin-Hsiang Lin, Chien-Wei Wang
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Publication number: 20220373891Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.Type: ApplicationFiled: July 25, 2022Publication date: November 24, 2022Inventors: Jing Hong Huang, Chien-Wei Wang, Shang-Wern Chang, Ching-Yu Chang
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Publication number: 20220353480Abstract: A projection apparatus with an automatic adjustment function and an automatic projection adjustment method thereof are provided. The projection apparatus includes a control device, a projection device and a ranging device. The projection device is coupled to the control device. The ranging device is coupled to the control device. The control device operates the ranging device to perform multi-point ranging within a projection range of the projection device and on a projection surface. The control device determines whether a position of the projection range is suitable for projection according to a plurality of first distance values of a plurality of detection points provided by the ranging device, so as to adjust the projection range. The projection apparatus has an effect of accurate and automatic projection adjustment.Type: ApplicationFiled: April 20, 2022Publication date: November 3, 2022Applicant: Coretronic CorporationInventors: Chien-Wei Wang, Po-Yen Wu, Chih-Lin Wang
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Publication number: 20220342491Abstract: A projector including a controller circuit and a shuttle wheel, and an operating method are provided. The controller circuit controls an operation of the projector. The shuttle wheel is disposed on an upper cover of the projector. The controller circuit controls whether the projector enters an on screen display mode according to an operation method of the shuttle wheel. When the projector enters the on screen display mode, the controller circuit controls the projector to project a first menu on a screen. According to the operation method of the shuttle wheel, the controller circuit selects an adjustment item of the projector on the first menu. When the projector does not enter the on screen display mode, the controller circuit controls the projector to project a second menu on the screen. According to the operation method of the shuttle wheel, the controller circuit sets the adjustment item on the second menu.Type: ApplicationFiled: March 24, 2022Publication date: October 27, 2022Applicant: Coretronic CorporationInventors: Hsiu-Min Hsiao, Chien-Wei Wang, Chih-Lin Wang
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Publication number: 20220295026Abstract: The invention provides a projector and a correction method thereof. The projector includes a ToF sensor, a calculation unit, a control unit, and a projection module. The ToF sensor senses distances between measurement points on a projection surface and the projector in a distance measurement operation. The calculation unit is coupled to the ToF sensor. The calculation unit calculates at least one distance ratio corresponding to at least one direction according to the distances, and obtains at least one offset angle in the at least one direction according to the at least one distance ratio. The control unit is coupled to the calculation unit and the ToF sensor. The projection module is coupled to the control unit. The control unit performs a keystone correction operation of the projection module according to the at least one offset angle.Type: ApplicationFiled: February 16, 2022Publication date: September 15, 2022Applicant: Coretronic CorporationInventors: Po-Yen Wu, Chih-Lin Wang, Chien-Wei Wang
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Patent number: 11442364Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.Type: GrantFiled: May 16, 2019Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jing Hong Huang, Chien-Wei Wang, Shang-Wern Chang, Ching-Yu Chang
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Patent number: 11422465Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.Type: GrantFiled: December 18, 2019Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Han Lai, Chin-Hsiang Lin, Chien-Wei Wang
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Publication number: 20220260918Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Chien-Wei WANG, Ching-Yu CHANG, Shang-Wern CHANG, Yen-Hao CHEN
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Patent number: 11320738Abstract: In a pattern formation method, a bottom layer is formed over an underlying layer. A middle layer is formed over the bottom layer. A resist pattern is formed over the middle layer. The middle layer is patterned by using the resist pattern as an etching mask. The bottom layer is patterned by using the patterned middle layer. The underlying layer is patterned. The middle layer contains silicon in an amount of 50 wt % or more and an organic material. In one or more of the foregoing and following embodiments, an annealing operation is further performed after the middle layer is formed.Type: GrantFiled: March 27, 2019Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Wei Wang, Ching-Yu Chang, Shang-Wern Chang, Yen-Hao Chen
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Publication number: 20220051315Abstract: Information regarding individuals that fit a bad performance definition, such as individuals that have previously defaulted on a financial instrument or have declared bankruptcy, is used to develop a model that is usable to determine whether an individual that does not fit the bad performance definition is more likely to subsequently default on a financial instrument or to declare bankruptcy. The model may be used to generate a score for each individual, and the score may be used to segment the individual into a segment of a segmentation structure that includes individuals with related scores, where segments may include different models for generating a final risk score for the individuals assigned to the particular segments. The segment to which an individual is assigned, which may be determined based at least partly on the score assigned to the individual, may affect the final risk score that is assigned to the individual.Type: ApplicationFiled: September 14, 2021Publication date: February 17, 2022Inventors: Chuck Robida, Chien-Wei Wang