Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A method for forming a patterned mask layer is provided. The method includes forming a layer over a substrate. The method includes forming a first strip structure and a second strip structure over the layer. The method includes forming a spacer layer over the first strip structure, the second strip structure, and the layer. The method includes forming a third strip structure and a fourth strip structure between the first strip part and the second strip part. The connecting part is between the third strip structure and the fourth strip structure. The method includes removing the spacer layer. The first strip structure, the second strip structure, the third strip structure, and the fourth strip structure together form a patterned mask layer.

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

Abstract: A method for forming a semiconductor structure includes forming first mandrels over a target layer. The method for forming a semiconductor structure also includes forming a first opening to cut off one of the first mandrels. The method for forming a semiconductor structure also includes forming a spacer layer over the first mandrels. The method for forming a semiconductor structure also includes forming second mandrels over the spacer layer and between the first mandrels. The method for forming a semiconductor structure also includes forming a second opening to cut off one of the second mandrels. The method for forming a semiconductor structure also includes etching the spacer layer. The method for forming a semiconductor structure also includes etching the target layer.

Abstract: Provided is a method for manufacturing integrated circuit (IC) devices including the operations of forming a first metal pattern (Mx) on a semiconductor substrate, forming a first via pattern (Vx) on the first metal pattern using an area selective deposition (ASD) that includes first and second vias formed adjacent opposed edges or terminal portions of the first metal pattern, and forming a second metal pattern (Mx+1) on the first via pattern with substantially no pattern overlap to form a zero enclosure and wherein a pair of adjacent vias are separated by a distance corresponding to the smallest end-to-end metal pattern spacing permitted under a set of design rules applied during the design of the IC devices.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: An integrated circuit includes a first active region, a first contact, a first gate, a first conductive line, a first conductor and a first via. In some embodiments, the first active region extends in a first direction. In some embodiments, the first contact extends in a second direction, and overlaps at least the first active region. In some embodiments, the first gate extends in the second direction, and overlaps the first active region. In some embodiments, the first conductive line extends in the first direction, and overlaps the first gate. In some embodiments, the first conductor overlaps the first contact, the first gate and the first conductive line, and extends in the first direction and the second direction. In some embodiments, the first via is between the first conductor and the first conductive line, and electrically couples the first conductor and the first conductive line together.

Abstract: A method for forming a semiconductor structure includes forming a hard mask layer over a target layer. The method also includes forming first mandrels over the hard mask layer. The method also includes forming a first opening in the first mandrels. The method also includes depositing a spacer layer over the hard mask layer and the first mandrels. The method also includes depositing a second mandrel material over the spacer layer. The method also includes planarizing the second mandrel material. The method also includes forming a second opening in the second mandrel material. The method also includes patterning and etching the second mandrel material to form second mandrels. The method also includes etching the spacer layer. The method also includes etching the hard mask layer and the target layer.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: A method for forming a patterned mask layer is provided. The method includes forming a first layer over a substrate. The method includes forming a first strip structure and a second strip structure over the first layer. The method includes forming a spacer layer conformally covering the first strip structure, the second strip structure, and the first layer. The method includes forming a block structure in the first trench. The method includes removing a first portion of the spacer layer, which is under the first trench and not covered by the block structure, and a second portion of the spacer layer, which is over the first strip structure and the second strip structure. The method includes forming a third strip structure in the second trench and the third trench. The method includes removing the block structure. The method includes removing the spacer layer.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.