Abstract: A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: A sensing system for a vehicle includes a first sensor at a forward portion of a side of the vehicle such that a principal axis of the first sensor's zone of sensing is rearward and sideward and at an angle relative to the body, and a second sensor at a rearward portion of the side of the vehicle such that a principal axis of the second sensor's zone of sensing is forward and sideward and at an angle relative to the body. Data sensed by the sensors when each sensor senses with at least two zones of sensing are communicated to a control, which determines the presence of one or more objects exterior the vehicle and within the zones of sensing of at least one of the sensors.

Abstract: The present invention is directed to a touch panel. The touch panel includes an optical layer disposed on a bottom surface of at least one peripheral edge of a transparent substrate. A light shielding layer is disposed on at least a portion of a bottom surface of the optical layer. A touch sensing layer is disposed below the transparent substrate and the light shielding layer.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: The present invention is directed to an ultrasonic detection device and detection method thereof. The ultrasonic detection device includes a processor and a transceiver module, whereby the transceiver module may be operated to enter an additional reception mode and receive a first ambient echo. The processor may analyze the first ambient echo and generate an analysis result. When the generated analysis result shows that the first ambient echo has a signal characteristic indicative of an interference source in the environment, the transceiver module may again enter the additional reception mode before a detection operation is performed. As a result, an elimination mode may be performed to correctly obtain or distinguish the corresponding reflected wave of the detection operation, thereby avoiding an error of operation, such as distance detection, due to the presence of an interference source.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.

Abstract: A touch electrode device includes first electrode lines and second electrode lines formed on a transparent substrate. An insulating block is disposed at a junction between a first conductive connecting portion of the first electrode line and a second conductive connecting portion of the second electrode line. At least one insulating line is extended from the insulating block and disposed along the first electrode line.

Abstract: A touch panel includes first electrode lines disposed along a first axis on a transparent substrate, adjacent first electrodes being connected via a first conductive connecting element. The touch panel also includes second electrode lines disposed along a second axis on the transparent substrate, adjacent second electrodes being connected via a conductive bridge. The conductive bridge includes low-temperature conductive material.

Abstract: A touch electrode device includes first electrode lines and second electrode lines formed on a transparent substrate. An insulating block is disposed at a junction between a first conductive connecting portion of the first electrode line and a second conductive connecting portion of the second electrode line. Insulating lines are respectively extended from the insulating blocks along the first electrode line, and are disposed in gaps between the first electrodes and the adjacent second electrodes.

Abstract: A touch panel includes a touch electrode layer disposed on a touch area of a transparent substrate, and a light shielding layer disposed on a boundary area of the transparent substrate. At least one inner edge of the light shielding layer has plural trenches filled with conductive material. A trace layer is disposed on the light shielding layer and is electrically coupled with the touch electrode layer via the filled conductive material.