Patents by Inventor Chien-Yu Chen

Chien-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12372396
    Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: July 29, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien Yu Chen, Meng-Kai Hsieh
  • Publication number: 20250234485
    Abstract: A manifold liquid drainage system includes a first liquid drain body and a manifold assembly. The first liquid drain body includes a first hollow flow channel and a plurality of first openings. The manifold assembly is fixed to at least one of the first openings and communicates with the first hollow flow channel, wherein the manifold assembly includes a pipe, a quick release joint, an electronic flow valve, and a control circuit board. The pipe is connected to one of the openings. The electronic flow valve is installed between the pipe and the quick release joint. The control circuit board controls the electronic flow valve to regulate the liquid flow through the pipe.
    Type: Application
    Filed: August 6, 2024
    Publication date: July 17, 2025
    Inventors: Yi-Le CHENG, Chien-Yu CHEN, Chih-Wei CHEN, Tian-Li YE
  • Patent number: 12360543
    Abstract: A reference voltage generator circuit includes: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled with each other and are located on a substrate, wherein the first transistor has a first conduction threshold voltage and a first rated voltage, wherein the second transistor has a second conduction threshold voltage and a second rated voltage, wherein the first rated voltage is higher than the second rated voltage; wherein the reference voltage generator circuit is configured to generate a bandgap reference voltage with temperature compensation according to a difference between the first conduction threshold voltage and the second conduction threshold voltage.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: July 15, 2025
    Assignee: Richtek Technology Corporation
    Inventors: Chien-Yu Chen, Li Lin, Cheng-Kuang Lin, Yue-Hung Tang, Ting-Wei Liao, Shao-Hung Lu
  • Publication number: 20250210097
    Abstract: A memory device includes a memory circuit, a redistribution layer and a resistor circuit. The redistribution layer is coupled to the memory circuit. The resistor circuit is coupled to the memory circuit. The resistor circuit includes a first resistor set and a second resistor set. The first resistor set includes a first resistor and a second resistor. The second resistor set includes a third resistor and a fourth resistor. After the first resistor and the second resistor are coupled in parallel and the third resistor and the fourth resistor are coupled in parallel according to an impedance value of the redistribution layer, the first resistor set and the second resistor set are coupled in parallel according to an impedance value of the memory circuit.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Inventors: Chien Yu CHEN, Po-Jen YANG
  • Publication number: 20250174986
    Abstract: An integrated circuit includes a power rail, a connecting pad, a first internal circuit, a second internal circuit, and an electrostatic discharge (ESD) protection circuit. The first internal circuit is coupled to the connecting pad through a first signal wire. The second internal circuit is coupled to the first internal circuit through a second signal wire. The ESD protection circuit is coupled between the second signal wire and the power rail. When charged-device model (CDM) ESD occurs in the integrated circuit, the ESD protection circuit conducts ESD charge on the second signal wire to the power rail.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Chien Yu Chen
  • Publication number: 20250166678
    Abstract: A memory device is provided. The memory device includes a first training circuit and a second training circuit. The first training circuit is configured to generate a first clock signal having a first pulse width according a command address (CA) training signal. The second training circuit is coupled to the first training circuit and is configured to adjust the first pulse width of the first clock signal to output a second clock signal having a second pulse width when it is determined that the CA training signal is not enabled.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 22, 2025
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien Yu Chen, Po-Jen Yang
  • Publication number: 20250140335
    Abstract: A system is provided. The system comprises test devices, a transport device and a data processing device. The test devices perform tests different from each other to a memory device and output test results of the tests. The transport device transports the memory device to the test devices and comprises a first storage device. The first storage device stores the test results and a list of a part of test devices that have tested the memory device. The data processing device stores fabrication data of the memory device. When the transport device determines that the memory device is defective according to at least one of the test results, the data processing device generates a report according the at least one of the test results and the fabrication data.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 1, 2025
    Inventor: Chien Yu CHEN
  • Publication number: 20250131974
    Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventor: Chien Yu CHEN
  • Patent number: 12279397
    Abstract: A cold plate is provided and includes: a casing formed with an accommodating groove; a base coupled to the casing to define an action space together with the casing, where the action space communicates with the accommodating groove; a heat transfer structure disposed on an inner side of the base for transferring a heat energy generated by a heat source in contact with an outer side of the base to a working medium in the action space; and a pump having a stator disposed in the accommodating groove.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 15, 2025
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Yi-Wun Chen, Ming-Yuan Chiang, Chien-Yu Chen, Mu-Shu Fan
  • Patent number: 12272592
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: April 8, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Patent number: 12217815
    Abstract: The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: February 4, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chien Yu Chen
  • Patent number: 12196610
    Abstract: A photodetecting device is provided. The photodetecting device includes a silicon substrate, a germanium absorption region, and a plurality of microstructures. The silicon substrate includes a first surface and a second surface. The germanium absorption region is formed proximal to the first surface of the silicon substrate, and the germanium absorption region is configured to absorb photons and to generate photo-carriers. The plurality of microstructures are formed over the second surface of the silicon substrate, and the plurality of microstructures are configured to direct an optical signal towards the germanium absorption region. A system including an optical transmitter and an optical receiver is also provided.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: January 14, 2025
    Assignee: ARTILUX, INC.
    Inventors: Yen-Cheng Lu, Yun-Chung Na, Shu-Lu Chen, Chien-Yu Chen, Szu-Lin Cheng, Chung-Chih Lin, Yu-Hsuan Liu
  • Patent number: 12200903
    Abstract: A heat dissipation device is provided and includes: a casing; a base unit combined with the casing to form a water collecting chamber, a water inlet chamber, an action space and a water outlet chamber; a heat transfer structure disposed on an inner side of the base unit; a water inlet pipeline unit communicated with the water collecting chamber; a water outlet pipeline unit communicated with the water outlet chamber; and a pump unit disposed outside the casing and the base unit, and connected with the water inlet pipeline unit and the water outlet pipeline unit, so as to drive a working medium.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 14, 2025
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Ming-Yuan Chiang, Mu-Shu Fan, Chien-Yu Chen
  • Patent number: 12171824
    Abstract: The present disclosure relates to a composition for inducing immune response comprising a glycoengineered antibody or antigen-binding fragment thereof that is specific for an antigen portion having a receptor binding domain (RBD) of a surface protein of a virus. The present disclosure also relates to an immune combination and a method for treating an infection by a virus.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: December 24, 2024
    Assignee: CHO PHARMA, INC.
    Inventors: Chung-Yi Wu, Chien-Yu Chen, Ju-Mei Li, Kuo-Ching Chu
  • Patent number: 12146506
    Abstract: A two-phase cold plate includes a base, an upper cover, a heat exchange cavity and a cooling fin module. The upper cover is installed on the base, the heat exchange cavity is formed between the base and the upper cover, and the cooling fin module is installed in the heat exchange cavity. The upper cover includes at least one nozzle module and a plurality of two-phase fluid channels. The two-phase fluid channels are respectively located on both sides of the nozzle module, and the nozzle module sprays a heat dissipating fluid to the cooling fin module, and the heat dissipating fluid flows along the cooling fin module to the two-phase fluid channels on both sides of the cooling fin module to cool the cooling fin module.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: November 19, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Chun-Ming Hu
  • Publication number: 20240365507
    Abstract: A fluid heat dissipation device includes a first cold plate, a first adapter and a fluid delivery pipeline. The first cold plate is used to cool a first heat source, the first adapter is connected to the first cold plate, and the fluid delivery pipeline is connected to the first adapter and fluidly communicated with the first cold plate to improve the production efficiency and quality of the fluid heat dissipation device.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 31, 2024
    Inventors: Chia-Hung LI, Chun-Chi LAI, Chien-YU CHEN
  • Patent number: 12113141
    Abstract: An optical sensing apparatus is provided. The optical sensing apparatus includes a substrate, one or more pixels supported by the substrate, where each of the one or more pixels includes an absorption region, a field control region, a first contact region, a second contact region and a carrier confining region. The field control region and the first contact region are doped with a dopant of a first conductivity type. The second contact region is doped with a dopant of a second conductivity type. The carrier confining region includes a first barrier region and a channel region, where the first barrier region is doped with a dopant of the second conductivity type and has a first peak doping concentration, and where the channel region is intrinsic or doped with a dopant of the second conductivity type and has a second peak doping concentration lower than the first peak doping concentration.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 8, 2024
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Chien-Yu Chen, Yen-Ju Lin
  • Patent number: 12101914
    Abstract: A coolant distribution unit includes a casing, a control module, a power supply module, a heat exchange module, an integrated pipe, and a fluid driving module. The power supply module is electrically connected to the control module, the integrated pipe includes a plurality of inlets and an outlet to collect and output a cooled working fluid, the fluid driving module is electrically connected to the control module and the power supply module, and the fluid driving module is in fluid communication with the heat exchange module. The control module, power supply module, heat exchange module, integrated pipe, and fluid driving module are all arranged in the casing.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: September 24, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Chun-Ming Hu
  • Patent number: 12098732
    Abstract: A liquid cooling head includes an upper casing, an impeller, a bottom casing and a skived fin cooling plate. The upper casing has an inlet and an outlet, the upper casing is fixed on the bottom casing, and the impeller is arranged between the upper casing and the skived fin cooling plate. In addition, the skived fin cooling plate is fixed on the bottom casing, and the impeller sucks the heat-dissipating liquid from the inlet and drives the heat-dissipating liquid passing through the skived fin cooling plate, upwardly passing through the impeller and then discharged from the outlet.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 24, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Mu-Shu Fan, Chien-Yu Chen, Ming-Yuan Chiang
  • Patent number: 12096581
    Abstract: A bolster is provided and includes a bottom plate including a side plate extending upwards from a side of the bottom plate and a holding portion bending inwards from an edge of the side plate, a pillar vertically provided on the bottom plate and adjacent to the holding portion, and a torsion bar including two end portions and a main body portion, where one of the two end portions is fixed in the pillar and restricted by the holding portion, and the main body portion is restricted by the side plate. The bolster can effectively reduce warpage and deformation of the bottom plate.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: September 17, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Yi-Wun Chen, Yun-Kuei Lin