Patents by Inventor Chien-Yu Chen

Chien-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11429799
    Abstract: The present invention extends to methods, systems, and computer program products for testing proximity card readers. Aspects include proximity card reader test bed environments configured to test proximity card readers with a plurality of proximity cards while minimizing human involvement. A proximity card reader can be tested to determine a likelihood of the proximity card reader functioning as intended over time and to determine proximity card reader compatibility with different proximity card formats. Proximity card reader failures (e.g., crashes) and incompatibilities can be detected in the testbed environment reducing the likelihood of deploying defective and/or incompatible card readers into operation.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Turing Video
    Inventors: Weiwei Chen, Chien-Yu Chen, Tian Xie
  • Patent number: 11424620
    Abstract: A three-phase expandable AC system based on battery reconfiguration and a control method thereof are provided. The system includes a reconfigurable battery array capable of connecting to a load or being tied to a grid, and having a plurality of battery array modules. The reconfigurable battery array may perform charging or discharging with respect to the load or the grid, and may perform one of operations including: generating a single-phase AC voltage corresponding respectively to outputs of the battery array modules; generating a three-phase AC voltage corresponding to three battery array modules selected from the plurality of battery array modules; and generating a plurality of three-phase AC voltages in parallel from the plurality of battery array modules, and merging the three-phase AC voltages in parallel to scale power.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 23, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Kai-Cheung Juang, Chien-Yu Chen, Horng-Jzer Shih, Tzi-Cker Chiueh
  • Publication number: 20220262835
    Abstract: A photo-detecting apparatus includes an absorption layer configured to absorb photons and to generate photo-carriers from the absorbed photons, wherein the absorption layer includes germanium. A carrier guiding unit is electrically coupled to the absorption layer, wherein the carrier guiding unit includes a first switch including a first gate terminal.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Chien-Yu Chen, Yun-Chung Na, Szu-Lin Cheng, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Publication number: 20220248570
    Abstract: A coolant distribution unit includes a casing, a control module, a power supply module, a heat exchange module, an integrated pipe, and a fluid driving module. The power supply module is electrically connected to the control module, the integrated pipe includes a plurality of inlets and an outlet to collect and output a cooled working fluid, the fluid driving module is electrically connected to the control module and the power supply module, and the fluid driving module is in fluid communication with the heat exchange module. The control module, power supply module, heat exchange module, integrated pipe, and fluid driving module are all arranged in the casing.
    Type: Application
    Filed: January 19, 2022
    Publication date: August 4, 2022
    Inventors: Chien-Yu CHEN, Tian-Li YE, Chun-Ming HU
  • Publication number: 20220239223
    Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220239224
    Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
    Type: Application
    Filed: January 2, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220238727
    Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Wu-Te Weng, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220224325
    Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220223464
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220189849
    Abstract: An electronic package includes an electronic component and a heat dissipation structure, wherein the heat dissipation structure has a plurality of bonding pillars, and a metal layer is formed on the bonding pillars, so as to stably dispose the heat dissipation structure on the electronic component via the bonding pillars and the metal layer.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Inventors: Jian-Dih Jeng, Chien-Yu Chen, Wei-Hao Chen
  • Patent number: 11363739
    Abstract: A liquid cooling head device includes a base, a cover covering the base, an inlet portion disposed on the base, an outlet portion formed on the cover, and a fluid pump having a housing and a fan blade. The base includes a diversion channel, an opening and a first chamber connected to the diversion channel and the opening. A second chamber is formed between the cover and the base, and connected to the first chamber through the opening. The inlet portion is connected to the first chamber through the diversion channel. The housing covers one surface of the cover, so that a third chamber is collectively defined by the housing and the cover, and connected with the second chamber and the outlet portion. The fan blade is located in the third chamber, and the diversion channel is located between the fan blade and the first chamber.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: June 14, 2022
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Chien-An Chen
  • Publication number: 20220174833
    Abstract: A bolster is provided and includes a bottom plate including a side plate extending upwards from a side of the bottom plate and a holding portion bending inwards from an edge of the side plate, a pillar vertically provided on the bottom plate and adjacent to the holding portion, and a torsion bar including two end portions and a main body portion, where one of the two end portions is fixed in the pillar and restricted by the holding portion, and the main body portion is restricted by the side plate. The bolster can effectively reduce warpage and deformation of the bottom plate.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Inventors: Chien-Yu Chen, Yi-Wun Chen, Yun-Kuei Lin
  • Publication number: 20220169710
    Abstract: The present disclosure relates to a modified antibody or antigen-binding fragment thereof that specifically binds to SSEA4; especially with a glycol-engineered N-glycan. The present disclosure also relates to a method for enrichment of cells with the modified antibody or antigen-binding fragment thereof.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Applicant: CHO PHARMA, INC.
    Inventors: YING-CHIH LIU, CHIEN-YU CHEN, JU-MEI LI
  • Patent number: 11348221
    Abstract: A wafer testing method adapted to test a thin wafer. The thin wafer is combined with a vacuum-release substrate to form a wafer-assembly, and the wafer-assembly is placed in a wafer cassette. The vacuum-release substrate is attached to a front surface of the wafer with an attaching force which is sensitive to air pressure. The method includes the following steps. First, taking out the wafer-assembly from the wafer cassette, then transferring the wafer-assembly to a warpage-detection-device and placing the wafer-assembly on a first stage of the warpage-detection-device. Then, detecting warpage of the wafer. If the warpage of the wafer is less than a warpage threshold, the wafer-assembly is taken out from the first stage, and the wafer-assembly is turned over to place the wafer-assembly on a second stage. Then, applying negative pressure to the vacuum-release substrate to eliminate the attaching force. Then, removing the vacuum-release substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 31, 2022
    Assignee: MPI CORPORATION
    Inventors: Chien-Yu Chen, Han-Yu Chuang, Po-Han Peng
  • Patent number: 11340398
    Abstract: A waveguide structure includes a first surface having a first width, a second surface having a second width, the second surface being opposite to the first surface, and a sidewall surface connecting the first surface and the second surface. The first width is greater than the second width.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 24, 2022
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Chien-Yu Chen, Han-Din Liu, Chia-Peng Lin, Chung-Chih Lin, Yun-Chung Na, Pin-Tso Lin, Tsung-Ting Wu, Yu-Hsuan Liu, Kuan-Chen Chu
  • Publication number: 20220157982
    Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.
    Type: Application
    Filed: October 20, 2021
    Publication date: May 19, 2022
    Inventors: Kuo-Chin Chiu, Ta-Yung Yang, Chien-Wei Chiu, Wu-Te Weng, Chien-Yu Chen, Chih-Wen Hsiung, Chun-Lung Chang, Kun-Huang Yu, Ting-Wei Liao
  • Patent number: 11337337
    Abstract: A dissipating device applied to an electronic device and configured to absorb the heat source generated by the electronic device. A thermal conductive fluid is filled in the dissipating device of the present disclosure. The thermal conductive fluid is a mixture of two immiscible fluid mediums. When the thermal conductive fluid contacts the heat source of the electronic device, the thermal conductive fluid will continuously undergo a phase transition cycle to speed up the heat dissipation effect of the dissipating device on the electronic device and achieve an excellent heat dissipation effect.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 17, 2022
    Assignee: THERLECT CO., LTD
    Inventor: Chien Yu Chen
  • Publication number: 20220143172
    Abstract: The present disclosure relates to a composition for inducing immune response comprising a glycoengineered antibody or antigen-binding fragment thereof that is specific for an antigen portion having a receptor binding domain (RBD) of a surface protein of a virus. The present disclosure also relates to an immune combination and a method for treating an infection by a virus.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 12, 2022
    Inventors: Chung-Yi WU, Chien-Yu CHEN, Ju-Mei LI, Kuo-Ching CHU
  • Patent number: 11329081
    Abstract: A photo-detecting apparatus includes an absorption layer configured to absorb photons and to generate photo-carriers from the absorbed photons, wherein the absorption layer includes germanium. A carrier guiding unit is electrically coupled to the absorption layer, wherein the carrier guiding unit includes a first switch including a first gate terminal.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 10, 2022
    Assignee: Artilux, Inc.
    Inventors: Chien-Yu Chen, Yun-Chung Na, Szu-Lin Cheng, Ming-Jay Yang, Han-Din Liu, Che-Fu Liang
  • Patent number: D956004
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 28, 2022
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Jen-Hao Lin, Tian-Li Ye, Chien-Yu Chen, Chien-An Chen